Issue

Key challenges and directions in the 2001 factory integration roadmap

01/01/2002

Jeff Pettinato, Intel Corp., Chandler, Arizona

Successfully realizing the potential of ITRS targets requires an integrated factory that takes full advantage of its technologies to achieve device feature size reductions, near 100% yield, wafer-size increases, and other manufacturing productivity improvements (see table). It also requires factories that produce the right products in the right volumes on schedule, maintaining cost per unit area of silicon, with faster factory ramp-up times. Agile, flexible factories are also vital so they can change with technology and business needs. The industry faces several challenges that must be overcome to continue its historical growth rate.

Factories are becoming more complex and difficult to integrate due to rapid changes in semiconductor technologies, as well as changing business requirements, market conditions, and accelerated ramp and yield targets. They now must incorporate an increasing number of new and different equipment types and software applications concurrently to meet multiple business objectives and customer requirements.

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Production equipment overall equipment efficiency (OEE) performance and extendibility are key cost and productivity issues. Bottleneck production equipment does not currently meet the 2001 OEE requirement of 75%, which has an enormous impact on capital and operating costs. The industry has also been unable to effectively reuse equipment and other costly assets due to the rapid introduction of new processes, materials, and equipment.

The industry must also quickly realize its 300mm conversion efficiencies to recoup large investments made for this wafer-size transition. Factories must quickly ramp into high-volume production, while achieving the efficiency targets that have been set. These efficiencies include >2.25x more die/wafer than 200mm; >30% cost/die reduction; 100% automated interbay and intrabay materials-handling system (AMHS) for operational flexibility and cost improvements; the ability to track and run different recipes for each wafer within a carrier for operational flexibility; and the implementation of equipment, carrier, and software interface standards to reduce integration time, cost, and risk.

Beyond 2007, post bulk CMOS and 450mm wafers represent key inflection points. These changes may lead to significant manufacturing paradigm shifts to meet novel device-manufacturing requirements, while continuing to improve manufacturing productivity. To position for this change, the industry must devote attention to well-timed research programs that reduce the risk and complexity of these transitions.

The ITRS defines the scope of factory integration to include wafer fabrication, wafer probe and e-test, chip assembly, and final product burn-in and test.

Technology requirements and potential solutions for factory integration are expressed through six domains or "thrusts":

Factory operations cover policies and procedures used to plan, monitor, and control production within a factory. This is the key driver of requirements for other thrusts.
Production equipment covers process and metrology equipment (including embedded controllers), and their interfaces to other factory elements.
Materials-handling systems cover transport, storage, identification, tracking, and control of direct and indirect materials.
Factory information and control systems include computer hardware and software, manufacturing execution and decision support systems, factory scheduling, control of equipment and material-handling systems, and process control.
Facilities include the infrastructure of buildings, utilities, and monitoring systems.
Probe and test includes equipment and manufacturing processes to test wafers and chips.

Integrated solutions that span these thrust areas are critical to implement technology defined in the ITRS into a high-volume factory. Key metrics and potential solutions include:

reducing hot and normal lot cycle times/mask layer by implementing direct transport systems for tool-to-tool moves, accurate factory forecast models, and integrated planning, scheduling, and dispatch systems tied to material handling;
running different recipes for each wafer within a carrier by implementing standards for wafer-level tracking and control on equipment-embedded control systems;
reducing cycle time from groundbreaking to first tool move-in through standardized design concepts and electronic collaboration during design;
reducing cycle time between first tool move-in to first full-loop wafer out by using e-diagnostics, equipment engineering systems, and standard equipment interfaces to facilities;
improving OEE by implementing e-diagnostics, advanced process control systems, and equipment-engineering systems that leverage rich data sources and the Internet;
improving AMHS system throughput for interbay and intrabay by developing a fundamental capability that permits an AMHS to transport hot lots and gate send-aheads and hand carries;
reducing the lead time for solutions to conform with standards, including supplier-user collaborations to develop standards and solutions in parallel, and automated test tools for systematic interface testing; and
decreasing production equipment install and qualification costs as a percent of capital cost through base-build construction standardization "design for tool install" emphasis and standard equipment connections.

An increasing amount of the industry's bandwidth must be directed toward making its factories more productive. Near term, the industry must focus on realizing 300mm efficiencies and improving OEE.

These efforts are driving the concept of an "e" factory, which is one that leverages the power of the Internet, rich data sources, and other enabling capabilities. This results in pervasive process control, equipment monitoring and on-line repair, efficient material storage, and rapid lot delivery with factory-wide scheduling and dispatching. Longer term, the industry must focus on preparing for post bulk CMOS and 450mm wafers through well-timed research programs.

Jeffrey Pettinato received his BSEE and MSEE at George Mason University. He is the US co-chairman for the factory integration TWG and manages the equipment and process control automation group at Intel Corp., 5000 W. Chandler Blvd., Chandler, AZ 85226; ph 480/554-4077, e-mail [email protected].