The crosscut challenges of the 2001 ITRS metrology roadmap
01/01/2002
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Alain C. Diebold, International Sematech, Austin, Texas
Metrology continues to be challenged by the accelerated introduction of new technology generations as well as new materials and structures (see the table). In addition, new measurement requirements, such as 3-D control for transistor gates and interconnect trenches, voids in copper interconnect lines, and killer pores in low-k dielectrics, are complicating the advance of existing technology. Several of these requirements were not well understood when the 1999 ITRS was assembled.
Lithography metrology
Lithography metrology is facing all of these challenges. In addition to the acceleration of improvements in precision, critical dimension (CD) measurements must become capable of controlling feature shape during manufacture. The measurement of CD at the bottom of undercut (notched) gate structures is one example of the need for 3-D shape control.
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CD-scanning electron micro- scopy (CD-SEM), scatterometry, optical CD, and CD-atomic force microscopy (CD-AFM) are all potential methods of CD control. Optical CD uses special test structures and an overlay system to control focus and exposure and thus CD. The metrology roadmap in the ITRS states that with continued advancement, CD-SEM remains a potential solution for CD measurements. Scatterometry has moved into manufacturing, where it can provide 3-D feature shape control.
In parallel, longer-term replacement microscopy methods such as the point projection microscope (electron holographic measurement of surface dimensions in 3-D) are considered potential solutions to CD measurement needs.
Measurement of mask CD remains a difficult challenge that requires the advance of optical microscopes used to measure CD. Other systems such as CD-SEM and CD-AFM are potential means of measuring mask CD.
The precision required for controlling CD depends on the allowed process range. The ITRS lists a 10% 3s process range for total CD variation, and agreements between various TWGs break this process range into two-thirds for lithography and one-third for etch. In 2003, a 0.9nm precision will be required to control a final gate length of 45nm for microprocessors. This will be a tremendous challenge for all CD measurement methods, and the future will bring even more difficult requirements as precision scales along with the CD.
An even bigger challenge will be controlling line-edge roughness (LER). LER has been correlated to the increase in transistor leakage current, but not to changes in drive current. This recent finding has led the lithography TWG to request a new specification for LER that requires a CD measurement tool to have an even better precision than that required for CD control. In 2003, LER imposes a precision requirement of ~0.7nm vs. the 0.9nm precision specification for CD measurement. This requirement is new enough that there are no standard methods of determining LER from a SEM image.
Overlay control will continue to be difficult due to future overlay metrology requirements and problems caused by low contrast levels. The need for new target structures was suggested in the 1999 ITRS as a means of overcoming issues associated with phase shift mask and optical proximity mask alignment errors not detectable with traditional targets. As requirements for tighter overlay control are driven by scaling, the line edge of overlay targets in interconnect is roughened by chemical mechanical polishing (CMP). Low-k materials used as insulators will continue to make overlay more difficult, especially as porous low-k moves into manufacturing.
FEP metrology
Although many front-end processing (FEP) metrology requirements were stated in the 1999 ITRS, continued development of measurement technology is required to meet these challenges. Measurement of the thickness of new transistor and capacitor materials, such as metal oxide dielectrics, is only part of the challenge. Controlling the interface below these high-k materials will be both critical and difficult.
Both optical and electrical measurements are being advanced, and methods used during R&D must be robust for manufacturing control. Control of doping processes now includes the ability to measure junction depth. FEP metrology needs include measurement of starting materials properties, such as particles with a much smaller 2nm edge exclusion starting in 2003.
There is a strong link between the metrology needs of lithography and FEP. The control of effective (electrical) gate length of microprocessor transistors requires simultaneous control of the range of physical gate length and the range of dopant dose and junction both across the chip and from chip to chip. The 3-D control of line shape impacts the location of doped structures, such as source-drain extensions. The message here is that one must determine the allowed process ranges from the electrical properties of the transistors and use metrology data management systems such as those described in the ITRS' yield management roadmap.
Interconnect metrology
Two new, difficult measurement challenges in the 2001 ITRS involve interconnect metrology. Although there are potential methods for detecting voids in copper lines, the requirement of controlling voids to 1% at one-forth the linewidth seems impossible. The roadmap also lists detection of "killer pores" (one-twentieth the linewidth) in low-k dielectrics as a new need. If one killer pore is at the edge of a trench, the barrier layer in that area may not form during processing. Pore size distribution determination is another need that will be difficult to provide in-line with high throughput. CD and feature shape control needs extend to low-k trench and via structures.
Test structures
Another challenge is the shrinking size of test structures in scribe lines. Also, correlation between test structure measurements and on-chip variation is often considered unsatisfactory. One report at roadmap meetings indicated that overlay test structures in scribe lines were considered poorly correlated to on-chip variations. Even so, other measurements must be done in scribe lines.
Alain C. Diebold is chair of the ITRS metrology TWG and a senior fellow at International Sematech, 2706 Montopolis Dr., Austin, TX 78741; ph 512/356-3500, e-mail [email protected].