Wafer-level challenges within the ITRS test roadmap
01/01/2002
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Don Edenfeld, Intel Corp., Hillsboro, Oregon
Wafer probe technologies face complex electrical and mechanical challenges driven by product specifications, test implementation requirements, test productivity goals, and reduced test cost demands (see table). Across the IC spectrum, these challenges include: higher frequency response (i.e., bandwidth), rising pin counts across tighter pitches and smaller pads or bumps, increasing switching currents, alternative pad or bump metallurgies, and increasing test parallelism. R&D of new or improved probe technologies is required to meet these challenges to ensure probing can provide reliable and cost-effective electrical contact to devices under test.
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Increased wafer-level test parallelism up to and including full wafer contact will be necessary to manage product cost and will be particularly important for products with test times proportional to design density, such as memories. Planarity and compliance to the wafer under test will be critical parameters to enable reliable contact and repeatable electrical performance.
Integration of diverse circuits — such as analog, rf, embedded volatile and nonvolatile memory, and high-performance logic — is expected to increase. These combinations in single-die SOCs or in a multidie package place additional focus on wafer-level test to identify defects. Fabrication processes that enable integration of large flash memory arrays on die with high-performance logic and analog circuits are emerging today. The lack of sufficient built-in self-test techniques for nonvolatile memories requires that these devices go through a traditional memory wafer-level test flow using memory test equipment as well as a logic or mixed signal wafer-level test using logic or mixed signal test equipment. The difficulties associated with operational optimization of this multi-insertion manufacturing test flow and the high unit cost require breakthroughs in test equipment design and device design for test (DFT) methodologies.
The low power and high integration demands of some consumer market segments, such as cellular and handheld computing, combined with the advent of low-cost multidie packaging solutions, places additional emphasis on wafer-level test to provide known good die (KGD). Final yield for these multidie solutions is the product of individual die yield and assembly yield in final component test. Increased yield of each individual die provides lower unit cost impact due to yield loss associated with the packaging process by decreasing the probability of combining a good die and a bad die in a package.
KGD requires a paradigm shift in test philosophy to enable high defect coverage during wafer-level test. Defect coverage is obtained through a combination of DFT and test equipment capability. Increased defect coverage typically results in an increase in unit cost due to increases in die area for DFT circuitry, test time, and, potentially, test equipment cost.
High-performance market segments, particularly in the optical communications domain, will place increased demands on wafer-level test. Final product form factors require KGD for integration into hybrid modules. The high interface frequencies associated with these products combined with the need for KGD result in increased demand for at-speed test in the digital or analog domain during wafer-level test. Dramatic improvements are needed in production wafer probe to enable a high bandwidth interface to a die for raw interface frequency as well as accurate performance testing.
Don Edenfeld received his BS and MS in electrical engineering from the University of Virginia. He is chair of the ITRS test TWG and a test engineer at Intel Corp., 2501 NW 229th Ave., Hillsboro, OR 97124; ph 503/613-2868, e-mail [email protected].