Increase device yield with FEOL dry-clean processes
12/01/2003
overview
Cleaning at the gate transistor and SAC modules with conventional downstream plasmas and wet cleans has been improved with dual plasma dry-clean processing. Etch polymer removal, resist strip, and surface preparation were enhanced with downstream MW plasma and RF-biased RIE processes with various fluorine-based chemistries.
Cleaning at the gate transistor and self-aligned contact (SAC) modules with conventional downstream plasmas and wet cleans has been improved with the incorporation of dual plasma dry-clean processing. Etch polymer removal, resist strip, and surface preparation were enhanced through downstream microwave (MW) plasma and RF-biased reactive-ion etch (RIE) processes with various fluorine-based chemistries. The post-etch polymers resulting from the polysilicon gate and SAC etches were converted into volatile or fluorinated water-soluble species via the ion-assisted reactions in O, H, OH, F, and N containing plasmas.
This dual plasma technology offers improved cleaning capabilities for the 130nm to 150nm technology nodes. Implementation has improved yield and device performance by reducing gate oxide loss and lowering contact resistance, and has simplified the wet-clean sequence by eliminating some HF cleans. Dry cleans have proven vital for the front-end-of-line (FEOL) manufacture of current and future technologies.
Introduction
Traditional FEOL cleaning and surface preparation typically involves a two-step approach: a high temperature (250°C) O2 plasma strip followed by a wet-clean sequence [1]. Improvements upon the traditional methods have been demonstrated with dual-power RF + MW fluorine-based dry plasma cleans, which optimize and simplify the wet-clean sequence. F-containing chemistries, CF4 or NF3, have been incorporated into O2/N2 photoresist cleaning processes at lower temperatures to remove post-etch, Si-containing polymeric residue due to significant disadvantages using the traditional clean approach. The use of aggressive chemicals — HF, H2SO4, HCl, H2O2, and NH4OH solutions in particular — can etch and damage device features. With the need to reduce gate oxide loss and minimize CD bias, eliminating or reducing these aggressive chemicals from the clean sequence is inevitable [2]. Improved cleans are especially significant as the industry moves to newer generations of devices needing gate oxides as thin as 10–15Å by 2004 and CDs less than 0.1µm for contact holes [3, 4].
Experimental
These dual plasma FEOL processes were developed in the Novellus PEP Iridia system, the details of which are discussed elsewhere [5, 6]. The chamber features a 1.8kW microwave (2.45GHz) plasma source to generate radicals downstream and an RF-biased platen (13.56MHz, 500W generator), which can be run independently or simultaneously. To minimize oxide loss and CD bias, these specific processes are run at a low temperature, below 100°C.
Gate poly-clean experiments with fluorine flow showed that a concentration of <3% fluorine was required to minimize oxide loss while targeting the removal of polymeric residues on the gate structures. The final plasma process consisted of an O2 MW + RF plasma with <3% fluorine for polymer volatilization and an O2-only RF plasma for photoresist removal at low temperature (<100°C). After the plasma clean process, the wafers were processed in a wet-bench DI water rinse to completely remove the modified polymers from gate structures and the wafer surface. After the clean sequence, an Optiprobe model ellipsometer was used to measure remaining oxide thickness in the open areas of the wafer.
Self-aligned contact clean experiments showed that a concentration of <2% fluorine was required to minimize CD bias of the contact while targeting the directional etching of 30–50Å of polymeric residue and damaged silicon in the bottom of the contact hole. The final process consisted of an oxygen plasma for photoresist removal at low temperature (<100°C) to minimize oxidation of residues, and a second step of a fluorine-based plasma process for polymer removal and surface treatment. After the plasma clean, the wafers were processed in a Piranha (sulfuric acid and H2O2, SPM) and SC1 (NH4OH, H2O2, and DI water) clean solution. In-line defects and particles were measured on a KLA-Tencor model AIT wafer-inspection system with capability to detect defects >0.2µm in size.
Plasma strip and clean process in FEOL applications
Post-polysilicon etch clean. Removal of polymers and resist after the polysilicon gate etch is often the most sensitive FEOL clean application due to gate oxide loss and gate leakage concerns. Removal of heavy polymer build-up on the top and sidewalls of the gate structure after etch processes has been demonstrated in previous work with RF + MW fluorine plasmas or with more traditional HF wet cleans [5, 6].
Dual plasma-source cleans offer several benefits. First, they increase the strip rates because the anisotropic component of downstream plasma is added to the process, providing additional ion bombardment [5]. Second, the dual plasma source enhances the residue-cleaning capabilities. It appears that the isotropic etch feature of downstream plasma is maximized with the aid of moderate anisotropic ions from RIE plasma so that a synergistic cleaning result is obtained.
 Figure 1. a) Normalized residual oxide comparison between the O2 + HF/SPM clean and the O2/F-based dry clean + DIW; b) within-wafer remaining oxide thickness range. |
There is an additional area of concern for the gate module tested in this study. The HF and Piranha wet-clean sequence induces an unacceptable oxide-thickness nonuniformity on the poly sidewall and the exposed silicon surface. This nonuniformity in remaining oxide after the poly-clean sequence (Fig. 1) resulted in lower yield and a shift in transistor threshold voltage (VT). Using a dual-plasma, fluorine-based plasma dry clean and strip, the resist and polymers can be volatilized without the need for a subsequent HF wet clean, therefore reducing variability in the residual oxide thickness. This improves device performance, minimizes VT shift, and improves yield. Split lot testing performed on 10 production lots showed that an average of 3% total die-yield increase was measured for the wafers processed with the dual-source, fluorine-based plasma + DIW rinse poly-clean process.
As shown in Fig. 1, the residual oxide thickness for the fluorine-based dry clean maintains >85% of the original gate oxide thickness in the open area of the die, while the wafers processed with the O2 resist strip and HF wet clean show that about 75% of the original gate oxide was removed. The within-wafer residual gate oxide nonuniformity had also improved to ≤2Å with the new dry-clean process compared to 2–18Å with the old HF wet-clean method.
Post-contact etch clean. The contact modules have multiple areas of concern for cleans integration. Since highly polymerizing processes are used to maintain selectivity in the contact etch, polymer removal can be difficult. Also, as device dimensions continue to shrink, CD bias control is becoming increasingly important. For the 90nm technology node, it is expected that CD variation will be targeted at <5nm for all sources of variation in the module [7].
Using an O2 plasma, followed by the low-percentage fluorine-based clean step, a more effective polymer removal was achieved than was capable with a standard oxygen- and nitrogen-based microwave plasma process. Improved polymer removal can be seen in Fig. 2, which shows the in-line defect monitor results. This reduction in defectivity led to another 3% gain in line yield improvement for 0.15µm technologies.
The final fluorine-based clean step serves a dual purpose: it removes post-etch residues and utilizes fluorine to etch the damaged Si from the bottom of the contact. This is more commonly referred to as the "soft silicon etch" or "silicon light etch" and eliminates the need for other pre-deposition surface treatments. The use of the soft silicon etch has continuously demonstrated tighter and lower distributions of contact resistance, as seen in Fig. 3.
It should also be noted that this new contact clean did not eliminate the need for the standard wet-clean sequence. While there may be potential to simplify the wet-clean sequence by reducing wet processing times or eliminating some wet steps, the key to increased yield and device reliability when combining dry and wet cleans is to find the most robust process sequence possible. In some cases, this can be achieved with dry plasma clean plus a DIW rinse, but in others, some form of a traditional wet clean will be required to provide optimal process integration [2].
Conclusion
Fluorine-based clean processes incorporating microwave downstream and reactive-ion etch plasmas have been developed and integrated into the gate poly and self-aligned contact FEOL strip and clean sequences. The improved yield and device performance in 150nm and 130nm devices has proven that fluorine plasma-enhanced processes can achieve superior clean results relative to wet cleans for the gate clean process, and superior clean results vs. a traditional O2/N2 strip process for the self-aligned contact clean. Other benefits include lower cost-of-ownership for cleans processing by eliminating some steps, and safer operating conditions by minimizing hazardous chemicals, which reduces environmental concerns.
Acknowledgment
Mark Matson is also an author of this article.
References
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Wes Graff received his bachelors in chemical engineering from Texas A&M U. He is a senior process engineer in the Surface Integrity Group at Novellus Systems Inc., 4000 North First St., San Jose, CA 95134; ph 408/943-9700, e-mail [email protected].
Eddie Chiu received his education in electrical engineering and computer science from the U. of California-Berkeley. He is the process manager for the Surface Integrity Group at Novellus Systems Inc.
Vinay Krishna received his masters in chemical engineering from Clarkson U. and his bachelors in engineering from Karnataka Regional Engineering College, India. He is a process development engineer at Cypress Semiconductor. E-mail [email protected].
Jennifer Merriam received her bachelors in chemical engineering from Iowa State U. She is a manufacturing engineering manager, responsible for oxide etch and dry clean at Cypress Semiconductor.
Peter Keswick received his bachelors and masters in material science and engineering from the U. of California-Berkeley. He is the R&D etch manager at Cypress Semiconductor.