Meeting deep silicon etch challenges for silicon MEMS devices
12/01/2003
overview
Production solutions are established using a cassette-to-cassette system with an enhanced set of processes tailored for volume production, including a signal-processing approach that can provide SiO2 sensitivity to load areas of 2% on 150mm SOI wafers, and a dry etch technology that undercuts and frees structures without resorting to polysilicon-on-oxide and subsequent wet etching.
The rapidly expanding MEMS market is in a phase requiring tool sets to satisfy R&D needs and offer flexible, robust, and cost-effective production solutions. One approach is to provide a low cost-of-entry R&D system with a set of processes appropriate for device feasibility and prototyping.
Processes have been developed in response to the variety of applications requiring fast silicon etch rates and improved smooth sidewall morphology. For example, microfluidic devices and optical switches often have features tens of microns in depth but with sidewall smoothness requirements in the tens-of-nanometers range. These types of devices can benefit from a new approach that forms extremely smooth sidewalls with scalloping <10nm deep and a silicon etch rate >7µm/min. For other applications, such as pressure and acceleration sensors, when silicon etch rate and profile are of greater importance, rates >12µm/min can be obtained.
Silicon etching and profile control
 Figure 1. SEM image of a feature 30??m wide and 40??m deep, etched at ~12 ??m/min. |
Silicon etch rate is a strong function of fluorine concentration during the etching step. High concentrations of free fluorine are obtained with large sulfur hexafluoride (SF6) flow rates and relatively large coupled power to dissociate the SF6. A fast etch rate is most economically achieved when pumping capability and power supplies match to the appropriate application. It is unfortunate that many etch rate discussions do not take place in the context of needed throughput or market demands. High etch rate is possible, however, while maintaining feature profiles without unnecessary tradeoffs to mask undercut or roughness. The table provides some examples of achievable etch rates and depths. Figure 1 shows a 30µm trench feature with vertical sidewall profiles at ~12µm/min. Etch rates approaching 20µm/min can be achieved with larger features.
 Figure 2. Effects of profile control on a free-standing structure a) without morphing and b) improved with morphing. |
The range of feature sizes and aspect ratios has made profile control a challenging issue. One way of handling this diversity is with morphing, when the etch parameters are changed automatically and smoothly during processing. By adjusting process variables such as pressure, gas flows, power, and others during etching, the profile can be adjusted to compensate for the mass transfer of reagents and products. Figure 2 shows an example in which the process has been "morphed" to provide a vertical structure.
Sidewall morphology
The Bosch process, generally accepted for deep silicon etching, results in the formation of "scallops" on the sidewall of etched structures. This manifestation of sidewall roughness is a direct consequence of alternating deposition and etch cycles. The timing of the steps in each cycle can be directly correlated to etch rate and sidewall roughness. Including additional gases, such as oxygen or nitrogen, to encourage more anisotropic etching is one way to address the roughness issue. Though this approach does reduce roughness, it is difficult to control and there is a loss in etch rate. Low-temperature etching may also be applied to the smooth sidewall problem; however, sensitivity to temperature variations makes implementation difficult.
Another method to improve sidewall roughness utilizes shorter etch cycles. The length of the etch cycle is primarily limited to the relatively slow response of the mass flow controllers (MFCs). Though fast digital MFCs have improved the situation, they may still be limited in their ability to stabilize gas flows and avoid a flow burst at the start of each cycle, either of which will affect process reproducibility and stability. Efforts to reduce the initial gas surge by maintaining a minimal flow rate during the "off" cycle cause process gas-flow overlap and have not produced processes that are <2 sec.
Recently, Unaxis Semiconductors developed a proprietary, fast gas-switching technique to control gas introduction into the processing chamber and, thus, to reduce sidewall roughness. Destabilizing flows are even eliminated with short step cycles, promoting smoother transitions between etch and deposition steps. It is possible to reduce step times to the limiting value of the gas residence time constants of the processing module. More rapid etch rates with smoother sidewalls can be achieved by avoiding wait steps for the pressure to stabilize.
Figures 3a and 3b show the correlation between the frequency of sidewall scallops with the etch rate. In conventional Bosch processing, the distance between the scallops increases as the etch rate increases. (Due to ease of measurement, the distance between sidewall scallops was used as a measure for the depth, or amplitude, of the scallops.) This figure also shows the improvement using the fast gas-switching technique where increases in etch rates do not increase sidewall roughness. In Fig. 3c–e, the results of this method are illustrated with scanning electron microscope (SEM) images. Smooth sidewalls with etch rates of ~7µm/min are possible with 100µm wide trenches, and etch rates >4.5µm/min are possible with trenches as small as 2.5µm in width. Process step times in the 0.5 sec regime, limited only by the module's residence time constant, can be implemented without expensive hardware.
Process pressure control
The cyclical process of deep silicon etching puts unique demands on common methods of pressure control. Typical closed-loop pressure control is inadequate as the etch and deposition steps become faster and faster. Throttling valves have difficulty responding to the pressure setpoints of the individual steps, and the response lag is reflected in poor pressure control. Reverting to open-loop throttle position control solves the problem partially, but there tends to be drift during long processes and poor wafer-to-wafer reproducibility, as seen in Fig. 4a. It is clear that over the process time measured pressure has drifted considerably and appears to continue to move out of compliance.
 Figure 4. Pressure control using a) throttle position setpoints and b) a proprietary algorithm combining pressure and position control. |
To provide a stable processing environment and avoid this pressure drift, Unaxis Semiconductors developed a proprietary algorithm. The pressure data presented in Fig. 4b shows the new control mode's effectiveness at maintaining accurate and stable process pressure.
Silicon-on-insulator endpoint detection
SOI processes require endpoint detection to avoid the effects of unnecessary over-etching. Aspect ratio (A/R) dependent etching (ARDE) occurs when etching features of different dimensions. As A/Rs (feature etch depth divided by width) become significant, the ability for mass transfer of reagents and byproducts in and out of the etched feature becomes limiting.
It is therefore common for high-A/R features to etch more slowly than low-A/R features. This characteristic affects SOI processes because larger features (with lower aspect ratios) will etch to the oxide insulator layer before the smaller features. During the overetching period, while the larger features "wait" for the smaller features to reach the oxide, the larger features may experience unwanted "notching" at the oxide-silicon interface. A sensitive method for detecting small amounts of oxide exposed during the etching is needed to counteract this effect. With sensitive endpoint detection, a switch to an SOI "finish etch" can occur as early in the process as possible.
 Figure 5. OES endpoint signal from SOI etching with 2% oxide exposed on a 150mm wafer. |
The cyclical nature of deep silicon etching makes it difficult for the conventional endpoint detection methods of laser reflectance interferometry and optical emission spectroscopy (OES) to be sufficiently sensitive. Through signal processing, however, it was possible to detect open oxide areas of <2% on 150mm wafers. Figure 5 shows an unambiguous endpoint signal that can be extracted from the wide variations of emission intensities from the etch and deposition steps.
Released structures
Etching microstructures, which are then released from the substrate, is most often accomplished by removing a sacrificial layer under the feature. A common approach uses polysilicon as the material for the desired feature and silicon oxide as the sacrificial layer removed with wet etching. Unfortunately, the properties of polysilicon limit the chemical, mechanical, and electrical performance, and thus a single-crystal material such as silicon is preferred. Without a removable layer to facilitate the release, a process flow called SCREAM (single-crystal reactive etching and metallization), developed at Cornell U., was modified to accommodate various applications.
 Figure 6. a) Released structure using SCREAM process; b) SEM of structure in the initial stage of undercut etching. |
In its simplest form, a structure is made by deep silicon etching (typically a Bosch-like process) using an oxide mask. Then oxide is deposited on the sides and bottom of the feature using PECVD. For very high-aspect trench structures, it may be necessary to use high-density PECVD to force oxide to the bottom of the trench. Following oxide deposition, another deep silicon etch process removes the oxide on the bottom (floor) of the feature. Finally, an isotropic etch process laterally undercuts the feature and releases it. Wet processes can be used in this step, but there is often a limiting crystallographic effect not seen with dry etching. The typical gas for dry etching is SF6. Figure 6 shows a diagram of the final structure and SEM of a feature being undercut.
Conclusion
Moving deep silicon etching from the exploration phase into production requires many manufacturing issues that go beyond the basic etch process to be addressed. Several of these include high etch rate for throughput, sidewall smoothness for device performance, pressure control for long-term process stability and reproducibility, and sensitive endpoint detection for low load conditions. There are always tradeoffs between performance and capital costs; it is important to have a good match between the process capability needed and production volume. To accommodate performance, volume, and cost needs, vendors are introducing manual load and cassette-to-cassette systems.
Acknowledgment
The authors wish to recognize co-author David Purser of Unaxis.
For more information, contact David Lishan, principal scientist, Unaxis Semiconductors, 10050 16th St. North, St. Petersburg, FL 33716; ph 727/577-4999, fax 727/577-7035, e-mail [email protected].