Defined film thickness leads to more MEMS on SOI
12/01/2003
overview
Microelectromechanical systems — also commonly referred to in Europe as microsystem technologies — are currently undergoing what can only be termed a revolution. An important component helping to drive this new wave is the growing shift from bulk silicon wafers to silicon-on-insulator (SOI), a 20-year-old material technology that is now making strides in chip manufacturing as chipmakers continue to recognize its ability to increase performance and functionality, as well as tackle power consumption problems.
MEMS are being employed for a growing array of widely disparate applications — everything from precision automobile airbag sensors to smart medical devices for microsurgery and biosensors used in high-tech security devices. Silicon is an ideal material for microelectromechanical systems (MEMS) manufacturing; its mechanical and electrical properties are precisely characterized, and the technology for microfabrication of parts in silicon is better understood than for any other material.
Many MEMS applications require surface micromachining, which entails the formation of layers of dissimilar materials on top of silicon wafers, followed by patterning and etching to fabricate specific structures. Silicon dioxide (SiO2) and polycrystalline silicon (polysilicon) are materials most commonly used for this operation. Polysilicon can be readily deposited on silicon wafers, and its relatively low cost makes it well suited for a variety of MEMS applications.
There are some specific challenges also associated with using deposited polysilicon films for MEMS manufacturing, however. These challenges include polysilicon's low thermal conductivity and roughness, film thickness (MEMS applications typically require thicker structures), and inherent stresses and stress gradients in polysilicon films that are detrimental to cantilevered structures with high aspect ratios, which are often used in MEMS applications [1].
There are two possible approaches to replacing polysilicon with single-crystalline silicon. The first is bulk micromachining, in which deep etching separates regions of the bulk wafer from the substrate; this technique is suitable for structures with vertical dimensions up to and even >100µm. Precise control of the etch depth is challenging in this case, however, and etching in the lateral direction under the MEMS structures is even more difficult. The second approach is to use SOI, which provides all the advantages of single-crystalline silicon, plus a well-defined film thickness that assures an accurate frequency of oscillation for the moving parts.
Tracing SOI's evolution
SOI technology was originally developed for the manufacturing of high-reliability electronics for the military and aerospace sectors, but currently it is used in mainstream high-performance ICs, such as very high-speed microprocessors. In parallel to electronic applications, SOI quickly captured the attention of designers of MEMS, optical MEMS (MOEMS), microphotonic circuits, and in other areas requiring similar material properties. The SOI structure, in which a single-crystalline silicon film is separated from the single-crystalline silicon substrate using buried amorphous SiO2, has many advantages for these kinds of applications.
 Figure 1. Sequence of steps in the Smart Cut process. |
The large-volume fabrication of SOI wafers is performed predominantly through the use of the Smart Cut approach shown in Fig. 1 [2]. The hydrogen implantation energy determines the thickness and uniformity of the single-crystalline silicon layer that is transferred from a "seed" wafer to another "handle" wafer. The seed wafer can then be recycled repeatedly for future manufacturing. The buried oxide is a conventional thermal oxide. Silicon film up to 1.5µm thick, with <5% (3s) thickness uniformity, can be readily obtained with standard implantation tools. Increasing ion energy >200keV enables the creation of thicker films, but it is usually simpler to use conventional epitaxial growth techniques on SOI wafers to extend the range of film thickness to several microns.
The advantage of this technique is that it is not limited to SOI. Other multilayered materials of interest to the MEMS community for which this process is well suited include silicon-on-fused silica, or quartz; silicon-on-glass; silicon carbide (SiC) on oxidized silicon; and indium phosphide (InP) or gallium arsenide (GaAs) on oxidized silicon, to name a few.
MEMS applications using SOI
 Figure 2. An example of a process sequence in micromachining of SOI wafers [3]. |
Fabrication of MEMS structures in SOI is similar to surface micromachining of silicon. One possible sequence of processing steps used by TRONIC's Microsystems, a French MEMS foundry, is shown in Fig. 2 [3]. It is simple to pattern and etch buried oxide under a relatively thin silicon film, and the film's single-crystalline nature makes it possible to grow a thick epitaxial silicon layer over it that provides both very low internal stresses and excellent mechanical and optical properties. The example shown produces a free-moving mass of silicon, suspended by thin torsion springs, that is highly sensitive to small accelerations. The motion of this mass is detected by a capacitor circuit and converted into a measure of acceleration. Similar structures are also used for gyroscopes.
Optical cross-connects
With the expansion of optical fiber communication and the advent of dense wave-division multiplexing (DWDM), the ability to manage hundreds or thousands of optical data streams propagating in bundles of optical fibers becomes critical. This includes a need to transfer light beams from any individual fiber in the incoming fiber bundle to any outgoing fiber. With this type of fiber cross-connection, new kinds of rerouting can be easily accomplished (e.g., setting up temporary optical links for special events, such as the Olympics), as can service restoration in the event of a fiber break somewhere in the network.
It used to be that such functions required converting optical signals to electrical signals, switching the electrical signals, and then regenerating the optical signals. In optical-only networks, light beams are redirected by a 2D or 3D array of micromirrors — typically, mirrors from 100–1000µm dia. spaced at approximately 100µm–2mm intervals.
Such arrays of small mirrors, numbering from a few dozen to a few thousand per chip, are best made by undercutting the single-crystalline silicon film in an SOI wafer. A schematic drawing of one such mirror suitable for a 3D cross-connect is shown in Fig. 3 [4]. In this example, the mirror is up to 1mm dia. and about 6µm thick. If made of polysilicon, keeping this thin sliver of silicon reasonably flat would be nearly impossible, since it is attached to the support frame by only two thin torsion springs. Stresses created in polysilicon film during deposition would severely deform the mirrors and distort the light beams reflected from their surfaces.
To fabricate the movable mirrors, the SOI film is first patterned to define the actual mirrors with gimbal rings and torsion springs. Then, silicon is removed from the backside of the wafer through anisotropic deep reactive-ion etching (DRIE, also known as the Bosch process, in which etch cycles alternate with polymer deposition on the etched sidewalls) [5]. Finally, the buried oxide is removed in a hydrogen fluoride (HF) bath, thus releasing the mirrors. The silicon film is usually coated with a highly reflective metal film.
To balance any possible stresses, the same thickness of metal, typically gold, is often deposited on both sides of the mirrors. To obtain mirror motion about two orthogonal axes, four electrodes are positioned under each mirror. In Fig. 3, the electrodes are placed on a second silicon wafer, which is bonded to the bottom side of the SOI wafer that contains the mirrors. Analog circuits control voltages applied to these electrodes to provide any tilt angle within a specified range.
Since the mirrors are made of a single-crystalline silicon film that is very uniform in thickness, and mirror and torsion spring dimensions are defined quite precisely by optical lithography, there is a high degree of uniformity of mechanical properties across the arrays, and tuning of voltages for individual mirrors may not be necessary. Since the mirrors are small and thin, they have a low moment of inertia and can switch light beams in 5–10 millisec.
Photonic waveguide switches
SOI substrates are highly useful for making optical waveguides and small optical switches, as single-crystalline silicon has good optical properties in the near-infrared light range. An SOI layer can be patterned into a waveguide, and several optical functions can be accomplished in an SOI chip. In conventional planar waveguides, the core is made of doped glass, and undoped glass is used for cladding. In SOI waveguides, silicon constitutes the core, and thermal oxide constitutes the cladding. Because the refractive index difference is very large for the Si/SiO2 system, the waveguide is smaller and can have very sharp bends, enabling the optical circuit to be an order of magnitude smaller than with conventional doped glass [6].
Small optical switches can also be made in an optical chip. A recent paper shows an example of a waveguide made in a polymer on top of an SOI wafer [7]. Surface machining of the SOI film and its release through etching the buried oxide produced a free-standing, cantilevered section of the waveguide, which can be coupled with one of two stationary waveguides using electrostatic comb drivers. In the near future, it should be possible not only to use SOI cantilevers as mechanical switches, but to propagate light inside them as well.
Other applications
Other products currently being made from SOI include pressure sensors for automotive applications and a new generation of mirrors for barcode scanning. The MEMS field is still relatively young and intensely competitive. Many key participants prefer to remain anonymous or will not disclose which specific technology they use.
In addition to purely commercial activities, there are numerous R&D MEMS projects in academia, industry, and government labs in the US, Europe, and Asia. Many of these research teams have adopted SOI as their primary starting material because SOI wafers are easy to work with, offer multiple advantages and are suitable for a variety of designs.
Conclusion
SOI wafers, consisting of two highly engineered films placed on a standard silicon substrate, are ideally suited for many MEMS applications. As SOI wafer production continues its rapid growth, many more applications of SOI to MEMS and MOEMS are anticipated. Moreover, since SOI wafers are becoming widespread in electronic applications, and SOI is well suited for optical waveguides, one can expect to see, in the near future, electronic and photonic functions fully integrated with MEMS on the same SOI substrate.
 Figure 4. Integration of light emitters and detectors with SOI-based MOEMS and transistors [8]. |
As a step in this direction, the MOEMS Manufacturing Consortium supported by the Advanced Technology Program (ATP) of the National Institute of Standards and Technology (NIST) has built a prototype of an integrated electronic/photonic device (Fig. 4) [8]. It is likely that many more integrated designs will follow, helping to further accelerate the widespread use of SOI material for fabricating a widening array of microtechnology devices.
Acknowledgment
Smart Cut is a registered trademark of Soitec.
References
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George K. Celler received his masters in physics from Warsaw U. and his PhD in physics from Purdue U. He has been affiliated with Bell Labs/AT&T/Lucent/Agere. Currently, Celler is chief scientist at Soitec USA, 2 Centennial Drive, Peabody, MA 01960; ph 908/665-8457, fax 978/336-0564, e-mail [email protected].