Targeting gate CD using feedforward APC and voltage control
12/01/2003
overview
A method of power delivery has been developed that reduces chamber-to-chamber CD variation by controlling the RF peak voltage in a high-density inductively coupled plasma reactor [1]. Advanced process control in the form of a feedforward loop was added and tested in a manufacturing environment, and improved lot-to-lot CD variation after gate etch relative to variations in the incoming lithography was demonstrated.
Each new generation of semiconductor devices demands tighter requirements for repeatability in wafer etching. At the polysilicon transistor gate, the quality of the etch is of particular importance because the final linewidth (i.e., critical dimension, CD) directly affects device performance. A final CD smaller than the targeted dimension can lead to higher leakage currents, Idd, and lower yield, while a larger CD may result in slower device speeds.
Sources of CD variation can occur within a wafer, from wafer-to-wafer, within a lot, from lot-to-lot, and between lots etched in different chambers. Within a wafer, nonuniformity is generally a consequence of reactor design and is determined by factors such as gas flow pattern, chamber symmetry, and plasma source configuration. Wafer-to-wafer and lot-to-lot variations may occur because of poor repeatability at all levels — equipment, process, and lithography on incoming wafers. All sources of variation must be minimized to achieve maximum production yield, requiring tight control of key process parameters in plasma etch systems. The most important of these is RF power.
RF power is needed to create the plasma discharge and provide the bias voltage that determines the energy of ions striking the wafer surface. This critical parameter, however, is poorly controlled in current commercial plasma etch systems. To maximize the efficiency of power delivery from the RF generator to the load, all RF plasma etch systems use a matching network to transform the load impedance so that it matches the output impedance of the generator. Because the amount of power lost in a matching network can be considerable, and it is not possible to determine a priori how much is actually dissipated in the plasma itself, control becomes a significant issue [2, 3]. Small variations in the hardware from chamber to chamber in the RF circuit can lead to differences in delivered power and, thus, differences in etch performance.
In a joint effort between STMicroelectronics and Lam Research Corp., a system has been tested that directly controls the peak RF voltage, Vpk, at the wafer chuck instead of the power at the output of the generator [4, 5]. The voltage, Vpk, is monitored with a voltage probe attached to the chuck, and its value can also be set as a recipe parameter. In the latter case, a feedback loop adjusts the output of the RF generator to maintain the required voltage. This approach allows direct control of the voltage delivered at the point of use — the wafer chuck — thus eliminating the impact of stray resistive and capacitive elements in the RF circuit between the chuck and generator. Variation in these strays, which include match resistance and capacitance between the wafer chuck and ground, is a major contributor to chamber-to-chamber mismatch [6, 7].
Once RF voltage control was engineered, its impact on CD performance in a manufacturing environment was investigated. Two aspects were studied. The first was to determine whether CD matching for wafers etched in different chambers was improved by direct control of voltage at the chuck. The second was the introduction of a novel feedforward technique. This was designed to improve lot-to-lot CD variation after etch by compensating for the incoming lithography variation on wafers.
Experimental
The etch system used in this study has a plasma source consisting of a flat spiral transformer-coupled plasma (TCP) coil that couples power inductively from an RF generator into the chamber. A second generator provides RF voltage at the wafer chuck. Both generators operate at 13.56MHz, their output locked in-phase. In the conventional mode of operation, the generator output power is the control variable. As noted previously, however, the matching network between the generator and the chuck is inherently inefficient, and the actual power delivered to the plasma is significantly less than the generator output power. In this new implementation, a voltage sensor is attached immediately below the chuck to monitor the peak RF voltage upstream of the match network. The desired chuck voltage can be entered as a recipe parameter, and a feedback control loop can be used to adjust the generator output to maintain that value. By operating in this mode, "point-of-use" control of the delivered peak RF voltage is maintained irrespective of any losses in the match.
Chamber-to-chamber CD matching
Polysilicon gate etching was conducted on two TCP 9400SE standalone systems and a TCP 9400PTX cluster chamber from Lam Research [8]. The results, however, are generally applicable to all of Lam's conductor etch systems that offer a voltage control option. Comparisons were made between voltage-controlled plasma etch systems and traditionally configured equipment. The gate stacks consisted of DUV resist, organic BARC, phosphorus-doped polysilicon, and gate oxide on 200mm wafers. On half of the wafers, an additional TEOS hard-mask layer was added between the BARC and polysilicon layers.
The nominal incoming CD after resist patterning was 0.35µm. Figure 1 shows a trend chart for etch CD data collected over a six-month period on two etch systems, designated A and B. During the first three months, approximately 100 lots were etched with the generator output power controlled in the conventional manner at 115W while the resulting voltage was monitored. Average voltage was found to be -290V. Between the two systems, the average final CDs differed by about 11.1nm. During the second three months, the two systems were switched to voltage control with the peak RF voltage maintained at -290V. The effect of point-of-use voltage control was significant, with the average difference in CDs between the two systems reduced by a factor of two, down to ~5.4nm.
Using conventional control methods, the distribution is bimodal as the first part of the trend chart in Fig. 1 shows, and the standard deviation of the combined data was 7.4nm. With voltage control, however, the distribution is more normal with the standard deviation reduced to 5.0nm, indicating a >30% reduction in chamber-to-chamber CD variation.
Effect of bias voltage on CD bias
To improve lot-to-lot repeatability, additional compensation for CD variation on incoming patterned wafers is required. One method is to feedforward CD data measured at the lithography step and adjust the etch recipe accordingly, but the relationship between some process parameters and CD must first be established.
 Figure 2. Linear dependence of etch CD bias on voltage at the chuck. |
Figure 2 shows the effect on etched CD bias when the peak RF voltage in each process step is varied by up to ±20%. As the voltage was increased, CD variations decreased linearly, with the final CD being smaller. This linear relationship was observed in all of the etch systems, suggesting that adjusting the CD bias to a target value can be achieved using a simple linear control function to adjust the peak RF voltage settings:
ΔCD = AΔV + B
where ΔCD is the required correction to achieve the CD target and ΔV is the necessary voltage offset. The implication of this linear relationship is that a feedforward control system can be established with the goal of reducing lot-to-lot CD variation from incoming lithography variations.
Feedforward CD control
Lot-to-lot CD matching with feedforward CD control was performed using peak RF-voltage adjustment at the wafer chuck as the control parameter. The intent was to minimize the standard deviation of the final CD from the desired target value. In order to set up the protocol for feedforward adjustment of CD, five bins, each 10nm wide, were defined for the incoming wafer lots based on the pre-etch CD. The total CD range covered was thus the target CD ±25nm.
For each bin, a recipe was created in which the bias voltage of each process step was set appropriately to give the CD bias required to bring the final CD to the target value. Each recipe was named according to the magnitude of the incoming CD relative to the target. For instance, an "L" condition had an incoming CD that was lower than target, whereas an "H" condition reflected a CD higher than the target. To demonstrate this method for improving CD performance, a series of lots were generated in which the incoming CD varied over a range of 38.1nm. This was accomplished by adjusting the exposure setting of the photolithography tool to give the desired lot-to-lot variation.
 Figure 3. Target vs. actual CD bias achieved using the feedforward peak RF-voltage algorithm. |
By applying the feedforward algorithm, the range in the outgoing etched CD was reduced to 14.4nm. In each lot, three wafers were measured, positioned at the front, middle, and back. The within-lot CD variation was found to be small, indicating that the feedforward algorithm can be based on the lot average CD value (Fig. 3). The close matching of the output CD from this feedforward test and the target CD indicates that the final CD after etch can be set accurately by choosing values for peak RF voltage in the etch recipe appropriate to the CD incoming from the photomasking operation.
 Figure 4. Cross-sections of transistor gates with initial incoming CD of 0.34, 0.36, and 0.38µm (from left to right) show profile is not affected. |
Figure 4 shows cross-sections for devices with incoming pre-etch CDs of 0.34, 0.36, and 0.38µm. This covers the full range of voltage adjustment of ±20% used to target the final CDs. The gate profiles are the same over this range, verifying that gate profile is not affected by varying the voltage in the etch process to adjust the final CD to target.
Feedforward in production
 Figure 5. Trend charts for a) incoming CD distance-from-target and b) final CD distancefrom-target, both over a six-month period in manufacturing. |
Following this initial demonstration, the feedforward algorithm was applied in a production environment. Data shown in Fig. 5a are of incoming CD distance-from-target measured over six months. During the first three months, ~80 lots were processed before the release of the feedforward method to production. At the time the feedforward method was introduced, a second lithography cell was brought on line, creating a larger incoming CD variation because of differences in the photo process between the two lithography cells (Fig. 5a). Despite the larger variation, the feedforward algorithm applied at the etch step effectively compensated for the 15nm difference in CD for wafers from the two lithography cells (Fig. 5b). The impact of the feedforward method can be seen in the distribution of CDs before and after etch. Before etch, the distribution is clearly bimodal with a standard deviation of 8nm, whereas after etch, the distribution is normal with a standard deviation reduced to 4.5nm (Fig. 6).
Conclusion
 Figure 6. Distribution plots for a) incoming and b) final CDs after implementing feedforward compensation. |
The benefits of this method of RF bias-voltage control can improve chamber-to-chamber matching performance by approximately a factor of two, and when incoming lithography CD data are factored in, lot-to-lot variations can also be reduced by almost a factor of two. The effectiveness of using CD information to adjust the etch recipe with a feedforward approach clearly improves CD bias repeatability, ultimately leading to improved production yield and device performance.
Acknowledgments
The authors acknowledge contributions to this work from James Darr, Qing May Lu, and David Flemming of STMicroelectronics. TCP and Voltage Control Interface are registered trademarks of Lam Research.
References
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Cindy Petronis received her BS in materials engineering from Rensselaer Polytechnic Institute and her MS in materials science and engineering from Lehigh U. She is a process engineer with responsibilities in both plasma and wet etch at STMicroelectronics, 1000 East Bell Rd., Phoenix, AZ 85022; ph 602/485-2303, fax 602/485-2955, e-mail [email protected].
Roger Patrick received his MA and D.Phil. in physical chemistry from the U. of Oxford. He is a director in the Conductor Etch Product Group at Lam Research Corp., 4650 Cushing Parkway, Fremont, CA 94538; ph 510/572 8300, fax 510/572 8523, e-mail [email protected].