Issue



Key process parameters for copper electromigration


11/01/2003







While many challenges of dual damascene copper metallization have been addressed, reliability poses a serious concern, especially as the device node shrinks to 90nm and smaller. Migration from Al- to Cu-based metallization, in conjunction with dielectric materials with lower permittivity, reduces the RC delay in interconnects; this enables the industry to continue scaling and to produce faster devices. Due to a higher melting point, Cu offers an obvious advantage over Al in terms of higher activation energy to diffusion, thereby sustaining a higher current density. Copper is a fast diffuser in dielectrics, however, and must be encapsulated by diffusion barriers on all surfaces.

Typically, a metal diffusion-barrier layer (MBL) of Ta or TaN or a bilayer is used inside features upon which Cu is deposited. The top surface of the copper exposed after CMP is usually covered with a blanket film of dielectric diffusion-barrier layer (DBL), such as SiCxNy or SiNx. Each of the interfaces plays a crucial role, because electromigration (EM) is a diffusion-assisted phenomenon. In addition, defects in Cu fill, such as voids, seams, and microstructural defects, may contribute to the overall failure process.

The Cu/MBL interface is key to resolving first-order issues with EM characteristics. The line-of-sight nature of PVD results in nonconformity of MBL along the sidewall and bottom of vias (the sidewall is thinner than the bottom), requiring deposition of a thick layer to achieve continuity of the metal barrier along the sidewall. A thick MBL at via bottom, however, is usually undesirable; it produces a flux divergence that causes early EM failure. Re-sputtering the barrier at the via bottom not only creates a continuous path for copper diffusion, but also enhances the sidewall coverage through deposition of .re-.sputtered barrier, thereby eliminating early modes of failure at the via/metal link interface [1].

The figure illustrates the difference in EM characteristics with and without a barrier re-sputter process. The failure distribution of specimens with barrier re-sputter is clearly monomodal with a low lognormal sigma (s = 0.3–0.5). This type of barrier layer has been combined with dielectric materials of differing k values (in the range of 3.6–2.7). The EM failure distributions consistently follow well-behaved lognormal distributions, demonstrating the extendibility of the barrier process for current and future-generation Cu-low-k interconnects (see figure).


EM failure distributions with different technology nodes and associated interlayer dielectric materials. Implementation of a re-sputter step after metal barrier deposition results in monomodal failure distribution. Performance for Black Diamond (BD) and the next-generation BD film with optimized barrier is comparable. The primary change is due to the shrink in interconnect dimensions going from 0.22 to 0.18 to 0.14µm.
Click here to enlarge image

null

The table summarizes the EM data with different technology nodes and the associated changes in interlayer dielectric materials. The extrapolated t0.1 lifetime at 105°C and 1MA/cm2 exceeds the specification of 10 years, which reveals robust EM performance of Cu low-k interconnects at 90nm. The failure lifetimes, however, are found to exhibit a decreasing trend with shrinking device dimension (see figure), suggesting potential reliability concerns with further scaling of devices, especially at 65nm and beyond.

Click here to enlarge image

null

There is general agreement among researchers that the Cu/DBL interface is the fastest diffusion path for Cu atom migration. In-house experiments show that the activation energy for EM failure (Q) is a function of the type of DBL (i.e., SiCxNy or SiNx or SiC) and is modulated by the interface adhesion energy between Cu and DBL. Furthermore, because copper oxidizes under ambient conditions, it is very important to treat the surface prior to DBL deposition. Both surface treatment and type of barrier layer play a large part in determining the interface adhesion energy. In-house experiments reveal that increasing interface adhesion energy from 3.5 to 10J/m2 results in an increase in Q from 0.66eV to ~1.04eV.

Similarly, Lane et al. report a linear relationship between Q and the intrinsic work of adhesion, arguing that the cleanliness and bond character at the interface have a significant impact on the diffusion kinetics of Cu [2]. EM characterization of specimens with a thin (<300Å) Co-P capping layer on a post-CMP Cu surface resulted in a Q = 1.25. Consequently, the failure lifetimes increased by an order of magnitude. A fracture energy calculation for the Cu/Co-P interface shows an adhesion energy value in excess of 20J/ m2 — much greater than that of Cu/dielectric capping materials. While metallic-capping layers may provide a solution to the EM challenges of future Cu interconnects, the deposition process must be selective without affecting other properties, such as intraline leakage, time-dependent dielectric breakdown, and stress migration.

Minimizing the thickness of the metal diffusion barrier at the via bottom while maintaining continuity along the via sidewall is essential to eliminate early modes of EM failure. The activation energy of EM failure is modulated by the interface adhesion strength between copper and the dielectric diffusion barrier layer. A metallic-capping layer improves the interface adhesion strength, thereby producing significant enhancement of EM activation energy and lifetime. Preliminary EM data of interconnects consisting of optimized PVD metal barrier with next-generation Black Diamond (BD) (k = 2.7) reveals comparable performance to that of BD having a k = 3.0, suggesting possible extendibility of the barrier process to next-generation low-k films. Failure lifetimes exhibit a decreasing trend with shrinking device dimensions; this suggests potential reliability concerns with further scaling of devices, especially at 65nm and beyond.

Acknowledgments

Black Diamond is a trademark of Applied Materials.

References

  1. G. Dixit, et al., Proc. International Interconnect Tech. Conference, IEEE, p. 162, 2003.
  2. M.W. Lane, E.G. Liniger, J.R. Lloyd, J. Appl. Phys., 93, 1417, 2003.

Deenesh Padhi is senior process integration engineer for BEOL integration at the Maydan Technology Center Group, Applied Materials; e-mail [email protected].