Wafer-level packaging update
11/01/2003
All projections show wafer-level packaging (WLP) to be a leading driver of the semiconductor packaging industry over the next few years, and the current level of activity and recent developments indicate that this is already underway.
Unit shipments of wafer-level packages are expected to nearly double in 2003, and growth will not slow down very much before 2007 [1, 2]. The table shows one set of projections for WLP volume by product type. The growth across all product lines indicates the broad proliferation of WLP that began a few years ago.
According to Jim Walker, VP of research at Gartner Dataquest, 2005 is the year that "WLP moves mainstream" [3]. Walker sees an upcoming packaging equipment boom being driven by WLP in 2004 and 2005.
Challenges being met
With the knowledge derived from decades of experience in frontend wafer processing, the packaging industry has a good understanding of the basic deposition and patterning processes for WLP. It is the more peripheral issues that are creating the current challenges. E&G Technology Partners have identified "several areas of WLP technology that, if further developed, could significantly expand [WLP's] applicability" [4]: bump compliancy, wafer-level burn-in and test, wafer thinning, wafer-applied reflowable underfill, and PCB design/cost.
Bump compliancy is one requirement that has been addressed by major suppliers in the industry. In July 2003, Kulicke & Soffa reported on a new WLP technology with a different structure at the base of the solder bump to improve reliability [5]. As shown in Fig. 1a, the previous structure, called "bump-on nitride" (BON), had only underbump metal and a redistribution layer between the solder bump and the wafer. The new WLP technology, Spheron WLP, is a "bump-on polymer" structure (Fig. 1b). The additional layer increases thermal cycling performance by 30% and improves the electrical performance by decreasing input capacitance.
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Some subtle issues leave room for more progress in solder bump reliability. Unitive Electronics recently published a study showing that existing models for electromigration in metallization on ICs cannot be extended in a straightforward manner to solder bumps [6]. Because of different grain structure and composition, the movement of material as current flows through it is different compared to aluminum lines. More work is needed to fully understand electromigration in the solder bumps typically used in WLP.
Wafer thinning and sawing
Wafer thinning and dicing processes, which have been around for decades, are showing new aspects due to WLP's nature. For example, a standard single pass sawing process has been satisfactory for ICs in conventional packaging, but the chipping and other defects that result from typical sawing processes are not acceptable for a packaging technology like WLP that leaves silicon exposed. It has been shown that a dual step sawing process reduces backside chipping to acceptable levels. Packaging subcontractor STATS, for one, has reported on extensive studies to optimize this process [7].
Wafer thinning technology involves numerous processes, including backgrinding, wet polishing, plasma etching, and chemical etching. Much of the motivation for evaluating processes results from reliability implications of thickness and backside finish on bare silicon ICs. A thinner chip can be more reliable because it can flex with the board it is mounted on, thus reducing stress on the solder joints. However, if scratches and other defects from the thinning process remain on the exposed surface, the devices are more susceptible to breakage. So, the thinning process must leave a smooth finish. A report from Motorola cites plasma etching as the preferred process [8], and a paper by subcontractor Siliconware identifies wet polishing as the best "cost-performance" process [9].
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WLP for RF, MEMS, and passives
Many new developments in WLP have occurred in RF and MEMS applications. WLP is particularly cost-effective for small die sizes with limited I/O counts, and this is often the case with RF and MEMS devices. Clarisay, for example, produces SAW filters, and a low-cost cavity package is created at the wafer level to house the devices [10]. Packaging is often cited as the largest component of MEMS device cost, so a wafer-level process flow for MEMS packaging is a high-leverage technology [11].
In the RF field, IMEC recently developed technology for adding functionality to RF devices with wafer-level processing. One recent paper described high-Q on-chip inductors created with WLP [12]. Other RF WLP developments involve new materials. Glass substrates, rather than silicon wafers, have been evaluated as the base material for WLP of RF devices. The characteristics of different glass materials create options for new configurations, including integrated antennas and EMI shielding [13].
Passive devices comprise a good portion of the WLP technology volume in the packaging industry. Passives can also be created on top of ICs (rather than as separate devices), accomplished by what has been described as "post-passivation layer" (PPL) technology [14]. This consists of dielectric and conductor layers added after standard wafer processes, much like redistribution layers for flip chip. The structures for passive components can be patterned in these layers above the chip.
Similar PPL technology can also be used to create thick copper layers on an IC for improved power distribution on the chip. Chip and package design really merge in this application. In most WLP technology, the packaging processes are simply added on top of chips after they are completed, but when packaging technology takes on some on-chip interconnect functions, the chip and package are not separate items.
Conclusion
It has been known for years that wafer-level packaging can provide significant cost and size benefits compared to conventional packaging technology. It has taken many product cycles for the technology and applications to develop to the point where WLP can really take off. These advances are happening now, and wafer-level packaging is on its way to becoming a mainstream packaging process.
Acknowledgments
Spheron WLP is a trademark of Kulicke & Soffa.
Jeffrey C. Demmin is a contributing editor to Advanced Packaging magazine, a sister publication. He can be reached at ph 408/383-3691 or e-mail [email protected].
References:
- Worldwide IC Package Forecast, Gartner Inc., July 2003.
- The McClean Report 2003 Edition, Mid-Year (July/August) Update, IC Insights Inc., July 2003.
- Jim Walker, Semicon West 2003 Gartner briefing, July 2003.
- Thomas Goodman, Peter Elenius, 2003 Pan Pacific Microelectronics Symposium, pp. 162–167.
- Scott Barrett, et al., "A New Wafer-level Package for Improved Electrical and Reliability Performance," 2003 IEEE/CPMT/Semi International Electronics Manufacturing Symposium.
- Glenn Rinne, "Time Dependent Materials Issues in the Electromigration of Solder Bumps," 2003 IEEE/CPMT/Semi International Electronics Manufacturing Symposium.
- T.G. Tessier, et al., "WLCSP Backend Considerations," 2003 IEEE/CPMT/Semi International Electronics Manufacturing Symposium.
- Li Wetz, et al., Proc. of the 2003 Electronic Components and Technology Conf., pp. 853–856.
- Larry Wu, et al., Proc. of the 2003 Electronic Components and Technology Conf., pp. 1463–1467.
- Neil Moskowitz, "Advanced Packaging Trends," pres. at the Advanced Pack. and Interconnect Alliance seminar, July 2003.
- Bob Markunas, Advanced Packaging, December 2002, pp. S11–S14.
- X. Sun, et al., Proc. of the 2003 Electronic Components and Technology Conf., pp. 1510–1515.
- A. Polyakov, et al., Proc. of the 2003 Electronic Components and Technology Conf., pp. 875–880.
- Thomas Goodman, "Opportunities Between Wafer Fab and Packaging," pres. at the Advanced Pack. and Interconnect Alliance seminar, July 2003.