Simplifying process integration using abrasive-free polishing
11/01/2003
Overview
To overcome complications of using traditional CMP high polishing pressure and abrasive content to minimize topography variations, a two-step, low-pressure polishing scheme is proposed. An abrasive-free slurry selectively removes copper with minimal dishing and is followed by a nonselective polish to maintain low topography.
The move to copper interconnects has forced fabs to abandon subtractive metallization techniques. While PVD provides precise thickness control for aluminum deposition, no such luxury is available with copper metallization. CMP gives only relatively crude control of copper thickness. In particular, the CMP step must control both the absolute copper thickness and the thickness variation, and these goals sometimes conflict.
null
Though the ideal process leaves the copper wires flush with the dielectric, such a result is difficult to achieve in practice. Use of traditional CMP high polishing pressure and abrasive content to minimize topography variation can complicate integration of low-k dielectrics. An extended polishing into the dielectric to remove topography variation can also result in unwanted loss of copper below specified tolerances. Even moderate dishing and erosion will reduce copper line thickness and increase interconnect resistance.
Topography challenges
CMP performance depends on the topography of the incoming wafer and details of the circuit pattern, as well as on process parameters. Arrays of dense lines tend to fill more quickly than sparse arrays or wide copper areas; as a result, dense arrays can have a much thicker copper layer, requiring more polishing to remove. Accelerants and levelers added to the plating bath attempt to minimize the topography of the copper layer.
 Figure 2. Topography comparison for wafers polished with abrasive and abrasive-free copper slurries. Barrier and oxide polish on all wafers used a nonselective slurry. |
null
Topography variations created by dishing and erosion can replicate themselves through the interconnect structure (Fig. 1). A dished-out copper region can create a depression in the subsequent dielectric layer. Copper from the subsequent metal layer may remain in this depression after CMP. Overpolishing into the dielectric during the barrier removal step with a low-selectivity slurry (LSS; slurry that removes copper and oxides at similar rates) removes these copper pools but also thins the surrounding dielectric. A certain amount of overpolish is often required to remove etch-induced "flaring" of the trenches and to maintain adequate spacing between lines.
When SiO2 is used, oxide loss resulting from overpolishing only affects the electrical performance of the circuit. With low-k dielectrics (k<3.0), however, the results can be disastrous. These materials are typically much softer than oxides, and may not be stable in slurry environments. Low-k materials with dielectric constants between 2.5 and 3.0 polish faster than oxide dielectrics, and faster material removal makes it more difficult to control the total dielectric loss.
null
Porous ultralow-k dielectrics (ULK) (k<2.5) often require a protective oxide cap layer to prevent moisture from penetrating the porous film. A thin cap layer is preferred in order to minimize the total dielectric constant of the stack, but the cap must be thick enough to protect the underlying material. Excessive overpolishing can require a thicker cap layer.
The total copper lost during the CMP step is the sum of any dishing and erosion, plus the thickness of dielectric lost during overpolishing. For predictable line resistance, the total copper loss should be as small as possible and should be consistent across the die area.
As feature sizes shrink, design rules limit aspect ratios; thus, lines become thinner and any material loss represents a larger fraction of the total. The 2001 edition of the International Technology Roadmap for Semiconductors calls for M1 trench depths at 90nm to be <0.2µm, with <10% thinning allowed.
Abrasive-free polishing expands process window
Many different parameters affect CMP performance. Polishing pressure and pad hardness affect the pad's ability to conform to wafer topography. Stiff pads are less prone to dishing and erosion because they don't bend. At the same time, stiff pads are less able to scour out pools of copper and other low spots. Also, topography variations created by high polishing pressure and high abrasive concentrations can be reduced in the barrier step, but total material loss increases. With ULKs, traditional CMP processes may require a thick oxide cap layer that increases the net dielectric of the stack. This cap layer should be as thin as possible to reduce its performance impact.
Slurry composition balances the chemical and mechanical aspects of CMP. A highly reactive slurry can be highly selective, dissolving away copper while leaving the other materials untouched. Alternatively, a chemically neutral slurry might rely entirely on mechanical action. Neither extreme is desirable. Chemically aggressive slurries are difficult to control and can corrode device patterns. Purely mechanical slurries tend to leave scratches and other defects. As a result of these dynamics, most slurry formulations try to balance the two effects.
Since copper is a soft metal, abrasive-free polishing (AFP) has attracted substantial interest. AFP uses chemical action to create a soft passivating surface layer. The polishing pad mechanically wipes the layer away, leaving an exposed copper surface. The copper then reacts with the polish chemistry to form a new surface layer. In contrast, abrasive-containing slurries rely primarily on mechanical action to physically remove the oxidized copper surface. Abrasive slurries tend to drive higher levels of dishing and erosion. Physical polishing is not sufficiently selective and will remove other materials that are not intended to be polished away. Furthermore, the introduction of slurry particles can cause scratching of the copper surface, especially if slurry particles agglomerate. Abrasive slurry selectivities are typically in the range of <30:1.
Because chemical action dominates AFP, these slurries are highly selective, enabling the removal of all the copper while stopping automatically on the underlying barrier layer, regardless of any copper thickness variations. The copper polish step does not touch the dielectric since the slurry chemistry does not soften the tantalum nor dielectric films, and there is no abrasive present to remove it. As a result, overpolish to remove excess copper does not cause dishing and erosion. AFP therefore helps minimize total copper loss (Fig. 2). Typical selectivity to tantalum for AFP slurries exceeds 1000:1.
 Figure 4. Polishing heads suitable for abrasive-free polishing incorporate through-pad slurry distribution. |
null
Many researchers have found that abrasive-free slurries do not work well on traditional rotational polishing tools. The slurry must insinuate itself into the space between the wafer and the polishing pad. We suspect that rotational polishing pushes the slurry ahead of the pad's leading edge (Fig. 3). The slurry does not reach the center of the pad, and copper removal slows or even stops. This effect is likely more pronounced at 300mm. It is not clear how slurry interaction between the pad and the wafer differs between orbital and rotational polishers, but empirical tests with orbital polishers and abrasive-free slurries have been more successful. Dispensing abrasive-free slurries through the polishing pad ensures even application of fresh slurry over the entire wafer surface. Through-the-pad distribution also minimizes slurry consumption by reducing slurry use (Fig. 4).
Once the copper has been removed, a nonselective polishing step with abrasives removes the barrier layer and smoothes any topography left by the copper polish. Less dishing and erosion means less polishing time for removal.
Oxide dielectrics have a relatively large process window within which to balance removal rate and topography control. The dielectric itself is mechanically and chemically stable. Low-k dielec-trics, especially ULK porous materials, are much softer and tend to adhere poorly. Stress induced by CMP can crack dielectric films and surrounding layers, or can cause catastrophic delamination. Also, scaling at smaller design rules reduces dielectric thickness. In combination, these effects make the CMP process window for ULK dielectrics unworkably small. By reducing dishing and erosion, AFP can recover more process latitude.
 Figure 5. Relationships between dielectric constant, modulus, polishing pressure, and time to delamination. |
null
In work conducted with Selete, it was found that delamination performance depends on the Young's modulus of the dielectric, the polishing pressure, and the polishing time [1]. Reducing pressure from 3.5 to 0.8psi decreased the propensity to delaminate by an order of magnitude. An ideal process minimizes both pressure and polishing time while still achieving acceptable results.
Selete demonstrated an 0.8psi process that met its needs for ULK integration, with acceptable removal rate, uniformity, and electrical performance (Fig. 5). A two-level copper interconnect structure with porous low-k (k=2.2) dielectrics suffered little dishing and no delamination. By minimizing copper loss, the process maintained the interconnect resistance specified in the design.
Conclusion
The recommended copper CMP process combines a two-step polish with an optimal tool architecture that supports orbital polishing and through-pad slurry distribution. First, an AFP selectively removes copper from the wafer, stopping at the TaN barrier layer. Low polishing pressure and lack of abrasive minimizes oxide erosion and dishing of wide copper areas.
The combination of low pressure and AFP minimizes the wafer topography so that a brief, nonselective polish is enough to remove the barrier layer and expose the underlying dielectric with minimal thinning. In this approach, slurry composition, slurry distribution, and process and polishing parameters all work together to minimize copper loss. Low-pressure AFP provides a wide process window and will allow integration of porous low-k materials for the 65 and 45nm technology nodes.
Malcolm Grief, Bob Hollands, Novellus Inc., Chandler, Arizona
Reference
- S. Kondo et al., "Low Pressure CMP for Reliable Porous Low-k/Cu Integration," Proc. of the ITTC 2003.
For more information, contact Malcolm Grief at Novellus Inc., Chandler, AZ; e-mail [email protected].