Issue



Challenges in gate stack engineering


10/01/2003







Overview

The rapid scaling requirements projected by the International Technology Roadmap for Semiconductors (ITRS) pose several key challenges that are very much dependent on device application. Though progress has been made in the areas of high-k gate dielectrics and metal gate systems, several issues remain — particularly scaling, threshold voltage control, and mobility degradation — and it is critical that the industry focus efforts to resolve them.

The ITRS outlines scaling trends for planar CMOS transistors for the next 15 years, with overall chip requirements driven mainly by the need for improvements in speed, power dissipation, and functional density [1, 2].


Figure 1. Effect of post deposition anneal ??? a) N2 600??C, b) N2 900??C, and c) O2 900??C ??? on the physical and electrical thickness of a 3.0nm HfO2 film.
Click here to enlarge image

null

Scaling requirements are dependent upon application, with logic chips defined by three main categories: high-performance (HP), e.g., high-end desktop and server applications, where maximized transistor speed is critical; low operating power (LOP), e.g., mobile or notebook computers, where performance requirements are high and battery capacity is somewhat large; and low standby power (LSTP), e.g., mobile phones, where performance requirements are less and battery capacity is limited.

The allowable leakage current is severely limited for both types of low-power logic, but it must be especially small for LSTP logic. With the rapid scaling projected by the ITRS, several key challenges must be addressed in order to meet these application-specific chip requirements.

Gate stack challenges

Major challenges in the front-end process (FEP) arena include the leakage current through the gate dielectric due to direct tunneling (direct tunneling current increases exponentially with decreasing gate dielectric physical thickness) and gate electrode depletion, especially for doped polysilicon (which becomes more significant with decreasing gate dielectric electrical thickness). The solutions being pursued to deal with these challenges are: 1) to significantly increase the relative dielectric constant, k, of the gate dielectric beyond the 3.9 value of silicon dioxide (high-k materials receiving serious consideration should exhibit k in the range ~9–25), which allows for an increase in the physical thickness of the gate dielectric and a subsequent reduction in the direct tunneling current and 2) to switch from a polysilicon gate to a metal gate electrode, which has virtually no depletion. Since CMOS optimization requires different work functions for PMOS and NMOS devices, it is likely that two different metals with different work functions, one for the PMOS and one for the NMOS device, will be needed, however. This will present additional difficult process integration issues, and is likely to increase chip processing complexity and cost.

Many high-k materials have been investigated over the past several years, with Zr- and Hf-based oxides and alloys receiving the majority of attention recently [3]. The industry trend has seen Hf-based materials as the preferred material system due to Zr instability in the presence of the polysilicon gate electrode (i.e., uncontrolled formation of metal silicide at the high-k/electrode interface).

Although a significant effort has been dedicated to the investigation of new gate dielectric material systems, several key issues must still be addressed before high-k materials can be implemented in a standard CMOS process flow. Among these, the most critical are equivalent oxide thickness (EOT) and gate leakage current scaling to meet ITRS requirements; threshold voltage control and stability; mobility/carrier degradation and their impact on saturation current; and reliability/gate oxide integrity (although not discussed in this article). None of these issues are mutually exclusive; that is, solutions to one or more of these issues can and have shown a possibility for either beneficial or detrimental effects on other material/.electrical performance parameters.

The scaling challenge

From the EOT vs. gate leakage current scaling standpoint, several factors are key in achieving acceptable results with high-k gate dielectrics: bulk material properties, deposition and curing (i.e., annealing) conditions, interfacial and capping layers (i.e., between the high-k gate dielectric and the gate electrode), and interfacial interactions due to subsequent thermal processing (between the high-k gate dielectric and the silicon channel as well as between the high-k material and the gate electrode).

Click here to enlarge image

null

The use of AL2O3 in the metal oxide systems (whether as a constituent of the bulk dielectric film or as a constituent of discrete interfacial layers) has resulted in significant scaling below 1.0nm EOT. Al-based materials, however, have been found to exhibit extreme charge-related issues resulting in unacceptable performance in both threshold voltage control and mobility. Indeed, AL2O3 is an extremely defective system. HfSixOy and HfSixOyNz exhibit improved thermal stability and increased crystallization temperatures compared to HfO2 [4], but suffer from a lower dielectric constant (which may ultimately limit their scalability to only a few technology generations).

Starting surface chemistry is significant for both the thickness of the lower interface and the quality of the starting materials. Previous results from atomic layer deposition (ALD) HfO2 have shown unacceptable defects below ~3.0nm physical thickness [5] due to the growth behavior during the ALD process, although the physical thickness limit may have some dependence on the starting surface.


Figure 2. Effect of the gate electrode material on the upper interfacial layer in a HfO2 gate stack; a) polysilicon and b) TiN/polysilicon.
Click here to enlarge image

null

Chemical oxides have proven to be a robust starting surface for high-k materials, with data indicating lower interfaces down to ~0.4nm [6]. NH3-based starting surfaces, including treatments on HF-last surfaces as well as chemical oxides (for interfacial layer k-value modification), have proven successful in reducing EOT by as much as 0.4nm compared to chemical oxide starting surfaces. Several experiments have indicated mobility degradation due to the NH3 treatments, while others have shown equivalent mobility between the chemical oxides and the NH3 pretreated surfaces. Further investigation regarding these effects is ongoing.

Capping layers have also proven to have a significant effect on scaling by suppressing reactions between the high-k gate dielectric and the gate electrode. The addition of a HfSixOy capping layer to HfO2 films has resulted in an EOT reduction by as much as 0.4nm, most likely due to a reduction in interfacial reactions between the polysilicon electrode and the high-k material. Post deposition annealing conditions also affect interfacial layer thickness as well as the EOT, as seen in Fig. 1.


Figure 3. Effect of the gate electrode material on the interfacial layer and effective k value in a HfSixOy gate stack. Note that the lower interface is shown to be below zero in the case of the TiN electrode. This is due to errors introduced by using nominal, rather than physical, oxide thickness.
Click here to enlarge image

null

One of the most dramatic effects on scaling comes from the use of metal gate electrodes. In the case of the following evaluation, a 10nm CVD TiN layer was deposited prior to the polysilicon gate electrode. This resulted not only in a significant reduction in the capacitance equivalent thickness (CET) due to elimination of gate depletion, but also in a significant (0.5nm) reduction in the EOT, due to the elimination of the upper interfacial layer (see table and Figs. 2 and 3). A brief summary of Hf-based high-k material scaling efforts over the past two years at International Sematech is shown in Fig. 4.


Figure 4. Scaling of various high-k and gate electrode materials.
Click here to enlarge image

null

Threshold voltage related issues

Other key issues with respect to the high-k gate dielectric system are threshold voltage control and threshold voltage instability. An asymmetric threshold voltage shift (i.e., 0.3V shift for NMOS devices and 0.9–1.0V shift for PMOS) has been observed for all high-k materials when utilizing polysilicon gate electrodes. MOS flat band voltage (Vfb) and threshold voltage (Vt) directions do not support the conclusion that this is solely due to fixed charge within the films or interfaces. Recent results point to Fermi level pinning due to metal-Si bonding at the upper interface [7], although charge trapping may also play a role.

Dopant penetration (particularly boron) through the gate dielectric and into the MOSFET channel must be addressed as well. Dopant penetration results in an uncontrollable shift in threshold voltage (in a positive voltage direction for boron penetration for PMOSFETs). Adding a relatively small amount of nitrogen to the high-k dielectric is expected to suppress the boron diffusion through the dielectric, as has been generally effective with current SiOxNy applications [8].

A possible solution to both of these issues is the implementation of metal gate electrodes, although Fermi level pinning has also been reported for materials with work functions close to either the conduction or valence bands [9]. Metal electrode materials with work functions near the mid-gap may suffer less from this Fermi level pinning effect [9]. Moving to fully-depleted silicon-on-insulator (FD-SOI) devices allows for near mid-gap metals, although threshold voltage control still requires a difference in work function for NMOSFET and PMOSFET devices. Such a strategy may be beneficial as it may be possible to adjust a single gate electrode material with ion implantation or some other technique (such as stoichiometry adjustment) to make the significantly smaller adjustment in work function required for these two device channel types.


Figure 5. Mobility trends for various high-k and gate electrode materials.
Click here to enlarge image

null

It has been found that, under DC conditions, fast transient charging occurs in high-k films, resulting in significant instabilities in threshold voltage and reduction in saturation current. Deposition technique, post deposition annealing, bulk and interfacial layer compositions, and integration schemes (i.e., high-k removal after gate etch or after spacer etch) apparently play key roles in determining the magnitude of charge trapping. HfSixOyNz has been shown to exhibit acceptable charge trapping characteristics [10, 11], while nonoptimized films, including some HfO2/HfSixOy stacks, experience large threshold voltage shifts and up to a 90% degradation in saturation current during as little as 0.5 sec pulse stressing.

The recent application of pulsed Id-Vg measurements to evaluate charge trapping within these films [12, 13] and its effects on threshold voltage instability and saturation current degradation has received significant attention. Charge trapping behavior can be demonstrated by varying the rise/fall time and width/height of the stress voltage pulses. Results from such testing do not address the question of the significance of charge trapping for CMOS operating frequencies in the GHz range.

Mobility issues

Mobility is also a key parameter influencing a number of transistor metrics, including saturation current, speed, threshold voltage, transconductance, and sub-threshold swing. Figure 5 represents mobility trends observed with several Hf-based high-k materials investigated at International Sematech. In general, it has been observed that mobility increases with decreasing high-k thickness (due to reduced total coulomb scattering due to charges in the high-k) while mobility decreases with the decreasing interfacial layer thickness (due to the reduced screening effect of the lower interfacial oxide).

Switching from polysilicon to TiN gate electrodes, however, has in some cases resulted in an apparent shift in the mobility trend line (i.e., for a given EOT, the TiN gate has a higher mobility than with polysilicon gate). This is attributed to a decrease in the upper SiO2-like interfacial layer (Fig. 2), which may have little effect on channel mobility due to remoteness from the channel/dielectric interface. Thus far, high-k gate stacks exhibiting electron and hole mobility equivalent to SiO2 with EOT<1.0nm have proven elusive.

One issue, however, is whether the calculated mobilities are a true measure of degraded channel mobility (e.g., by such effects as soft phonon scattering [14, 15]) or are an artifact of either carrier degradation (i.e., trapping) or the calculation methodology itself. With gate stacks in the EOT range of interest, carrier mobility extraction has proven to be challenging due to inaccuracies in the determination of the inversion charge density as well as degradation in the drain current measurements due to significant gate leakage currents and charge trapping. Various correction techniques have been proposed [16, 17] and are currently under evaluation. Charge trapping can result in an overestimation of the inversion charge and the underestimation of channel mobility.


Figure 6. The effects of a) pulsed Id-Vg measurements on b) the mobility estimation (10x1µm devices).
Click here to enlarge image

null

Compensation must also be made for high gate leakage current effects, which affect Id-Vg measurements and also result in an overestimation of inversion charge and underestimation of mobility in the high-field regime. Application of the pulsed Id-Vg technique to estimate accurately trap-free channel conductance and a charge pumping technique [13] to determine the true inversion charge appear to result in an estimation of channel mobility very close to the universal mobility curve for the Si/SiO2 interface (Fig. 6). Thus, charge trapping may actually be resulting in carrier depletion rather than mobility degradation (at least not to the magnitude previously thought).

Conclusion

Progress has been made in the areas of high-k gate dielectric and metal gate systems, although several key issues await resolution. Most of the detrimental effects observed with high-k materials may be attributed to charge trapping or fixed charges both at the interfaces and within the high-k bulk. The majority of work will focus on determining the causes for this trapping behavior and whether the defects associated with these fixed charges or trapping centers are intrinsic or extrinsic to the high-k material system. From both the scaling and threshold voltage control standpoint, it is critical that the industry focus efforts on implementation of metal gate electrodes, if not before high-k, at least in conjunction with high-k gate dielectrics.

Robert W. Murto, Mark I. Gardner, George A. Brown, Peter M. Zeitzoff, Howard R. Huff, International Sematech, Austin, Texas

Acknowledgments

The authors would like to thank Joel Barnett, Gennadi Bersuker, Nirmal Chaudhary, Sundar Gopalan, Jim Gutt, Alex Hou, Craig Huffman, Yudong Kim, Byoung Hun Lee, Choong Ho Lee, Hong-Jyh Li, Chan Lim, Pat Lysaght, Naim Moumen, Jeff Peterson, and Chadwin Young for their efforts as a part of the International Sematech gate stack team and the International Sematech ATDF for supporting our processing requirements. The authors would also like to acknowledge the SRC FEP Research Center and IMEC for their collaborative work with International Sematech in advanced gate stack research.

References

  1. Semiconductor Industry Association (SIA), International Technology Roadmap for Semiconductors, 2001 edition, Austin, TX; International Sematech, 2001.
  2. Semiconductor Industry Association (SIA), International Technology Roadmap for Semiconductors, 2002 edition, Austin, TX; International Sematech, 2002.
  3. H.R. Huff, et al., "High-k Gate Stacks Into Planar, Scaled CMOS Integrated Circuits," presented at the Conference on Nano and Giga Challenges in Microelectronics, Sept. 2002, to be published in Microelectronic Engineering, 2003.
  4. M. R. Visokay, et al., Applied Physics Letters, Vol. 80, No. 17, p. 3183, April 2002.
  5. T. H. Hou, et al., ECS Meeting, Volume 2002-2, Abstract No. 384, Oct. 2002.
  6. W. Tsai, et al., VLSI Tech. Digest, Session 3A-3, June 2003.
  7. C. Hobbs, et al., VLSI Tech. Digest, Session 2-1, June 2003.
  8. M. A. Quevedo-Lopez, et al., Applied Physics Letters, Vol. 82, No. 26, p. 4669, June 2003.
  9. Y.-C. Yeo, Electron Device Letters, Vol. 23, No. 6, p. 342, June 2002.
  10. A. Shanware, et al., International Reliability Physics Symposium Proc., p. 208, March 2003.
  11. S. Inumiya1, et al., VLSI Tech. Digest, Session 3A-1, June 2003.
  12. A. Kerber, et al., International Reliability Physics Symposium Proc., p. 41, March 2003.
  13. A. Kerber, et al., VLSI Tech. Digest, Session 12A-1, June 2003.
  14. M. Fishetti, et al., Journal of Applied Physics, Vol. 90, No. 9, p. 4587, Nov. 2001.
  15. T. Yamaguchi, et al., IEDM Proceedings, Session 26.3, p. 621, Dec. 2002.
  16. T. P. Ma, private communications (work by W. J. Zhu, et al.), May 2003.
  17. P. Zeitzoff, et al., Electron Device Letters, Vol. 24, No. 4, p. 275, April 2003.

Robert W. Murto and Mark I. Gardner are on assignment from Texas Instruments and Advanced Micro Devices, respectively. For more information, contact Murto at International Sematech, Austin, TX 78741; [email protected].