Planarizing difficult topographies using contact planarization
10/01/2003
Overview
Chemical mechanical planarization has the ability to planarize interlayer dielectric layers, tungsten layers, and even metal layers of aluminum and copper to adequately meet current industry needs. However, its compatibility with fragile low-k materials used in copper dual damascene processes is questionable. CMP is also undesirable for many compound semiconductors, for silicon processes where features are both dense and isolated within the same chip, and for many microelectromechanical systems applications. This article describes contact planarization, an alternative to CMP and a planarization technique that has exhibited both global and local planarization and demonstrated flat, uniform films over both isolated and dense features.
In the first step of contact planarization (CP), a malleable coating is applied onto the dielectric layer. Planarization materials are selected based on their ability to provide plasma-etch rates equal to those of the underlying dielectric material. Examples of planarization materials include epoxies, acrylics, vinyl-based chemistries, and silicon- or metal-containing organometallics. The coating may also be a dielectric material that can be applied and directly pressed, such as butylcyclobutene (BCB, Dow Chemical Co.), various polyimides, low-k materials, and spin-on glasses. When these functional dielectric materials are used, a subsequent etch-back process is not required because the planarized dielectric will remain as part of the device being manufactured.
In step two, the coated substrate is pressed against an optical flat surface to planarize the coating layer. The coating is then cured by either transmitting ultraviolet (UV) light through the transparent optical flat surface or by heating.
If the planarization layer is a dielectric material intended to form part of the device, the process is finished and ready for the cure cycle required for the dielectric. If a sacrificial planarization layer is used, the layer is uniformly etched away by a plasma-etching process. Etch processes can be tailored to provide a 1:1 selectivity between the sacrificial planarization film and the underlying material. The etching process continues until the topography in the underlying layer surface has been removed to yield a fully planarized device substrate. By using selected sacrificial planarization materials and modifying the etch formulations, this process can be applied to the full range of organic, inorganic, and hybrid dielectrics as well as to metal and semiconductor layers such as polysilicon, silicides, aluminum, and tungsten.
Experimental
To carry out this process, a dielectric topography substrate from SKW was used [1]. Also, areas containing line densities varying from 0–96% on a blanket plasma-enhanced tetraethylorthosilicate (PETEOS) layer over a patterned nitride/aluminum/Ti-nitride stack were used. The target topography was ~1.0µm. Figures 1 and 2 show the stack layout and die map, respectively. A sacrificial material containing a UV cross-linking polymer, UV photo initiator, and solvent was spin-coated onto the substrate and applied at process conditions that resulted in a 1–3µm film thickness on flat silicon wafers. Spin conditions were 1000–3000rpm for 45 sec. To prevent material from being pressed off the substrate edge, an edge bead of 4–5mm was removed, resulting in a 2–3mm edge bead after pressing.
 Figure 1. SKW 1-1 dielectric oxide CMP characterization wafer stack [1, used by permission]. |
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 Figure 2. SKW 1-1 dielectric oxide CMP characterization die floor plan. The step height in all feature density areas is 1µm [1, used by permission]. |
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The sacrificial material used required no bake step before being pressed and hardened. The coated wafer was placed in the press chamber, which was evacuated to about 500mtorr to remove residual solvents and other volatiles and prevent bubble entrapment during the press step. A vacuum was applied for 15–30 sec prior to pressing. Next, the press cylinder was activated to press the substrate against the optical flat surface. Press pressure against the optical flat surface was maintained for 15–60 sec. Then the coating material was exposed to UV light to harden the sacrificial material. It was critical that the material be hardened prior to separation to avoid destroying the surface quality. Topography measurements were taken with a Dektak 8 profilometer and scanning electron microscope (SEM) cross-section images were taken to evaluate planarity. Topography measurements were taken on an uncoated control wafer, a wafer coated with the sacrificial material and UV cured without the press step, and a substrate that was coated then pressed.
Results and data
Topography scans and film thickness measurements were taken on all of the feature densities of an SKW wafer after coating but without pressing, and after pressing. The uncoated wafer has an original feature height of ~1mm.
Figure 3 shows that CP exhibited excellent local planarization over the full range of densities found on a standard 6-in. CMP test wafer. This is compared to the planarization achieved with only spin-coating the wafer without pressing. In the case of the press-planarized sample, the step height over a feature remains constant at about 250Å regardless of the feature density. The unpressed wafer, however, shows a clear feature density dependency with larger step heights as the feature density approaches 50%, and lower step heights as the feature density approaches 0% and 100%. Additionally, SEM pictures (Figs. 4 and 5) show a uniform film thickness over different feature density areas for the press-planarized wafer, while the unpressed wafer shows a significantly thicker film over the high-density areas than over the low-density areas.
 Figure 3. Step height over structures for all feature densities of an SKW CMP wafer. |
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Isolated vs. dense features
Isolated (iso) and densely packed (dense) features often occur in the same chip. These features can be of several types, including vias that connect one layer to another. After spin coating, iso areas have significantly greater film thickness above the vias than do the dense areas because of the amount of coating material that flows into the vias, which leads to nonuniform planarity or a step when moving from the iso to the dense areas. CP can correct this by using a flowable material spun onto a patterned via wafer and pressed as described above.
A planarization experiment
An experiment was developed to determine a procedure for planarizing the via wafers. Because film thickness over the vias must be as thin as possible, a film thickness target of <0.5µm was set. This test was conducted using a bottom antireflective coating (BARC) solution to coat 8-in. IMEC contact via wafer quarters. The via wafers contained 0.25µm vias that were 1.2µm deep and consisted of areas of iso, dense, and semi-dense via patterns.
 Figure 6. Dense (left) and iso (right) areas of a pressed via wafer. |
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One via wafer quarter was coated with the BARC solution at the following conditions: spin speed 1 = 2500rpm, ramp = 6000rpm/sec, and time = 45 sec. The via wafer was pressed at the following conditions: press time = 60 sec, and press pressure = 60psi
The wafer was then cured with a 5-min UV exposure; results are shown in Fig. 6. After curing, the film thicknesses over iso and dense areas were compared using a SEM.
CP has been shown to enhance planarization under two difficult conditions. The process is likely to provide advantages in other applications where CMP fails to provide an ideal solution, including planarizing organic low-k dielectrics, nonsilicon substrates such as gallium arsenide (GaAs) and indium phosphide (InP), and other compound semiconductor materials. CP also has the potential for use in microelectromechanical systems (MEMS) applications, where high-aspect-ratio features are common.
Organics
Silicon chip manufacturers have determined that the interlayer dielectric (ILD) must be low-k to achieve continually smaller feature sizes. In order to decrease the k value further, ILDs are now being made porous. Using CMP to planarize such fragile materials has been described as being akin to "using sandpaper on gelatin." Other integrated circuits not made on silicon substrates use similar organic materials for dielectrics. Compound semiconductors, made mostly from GaAs and InP substrates, commonly use BCB as an ILD. Their topographies, mostly over features at least 0.25µm in size, have high aspect ratios. Those of GaAs chips can exceed a 5:1 height-to-width ratio. Because BCB is an organic low-k dielectric, it is difficult to planarize with CMP.
Other areas of IC chip manufacture that cannot use CMP include most backend processes. With the spread of flip chip and wafer-level packaging, the need for a more planar packaging layer has arisen. Again, the material of choice for passivation and packaging is BCB.
MEMS
MEMS have small features, and therefore their production requires many of the same manufacturing techniques developed originally for silicon semiconductors. MEMS devices can have numerous moving parts, can include multiple activities on the same chip, and can have extremely high aspect ratios. For MEMS, silicon is often used both as a mechanical substrate, which is adapted to achieve fluid flow dynamics, and as a semiconductor, which acquires electrical signals and passes them on to more standard data processors. These MEMS characteristics make it difficult to standardize production.
Aspect ratios for some MEMS devices can reach 50:1, which is unsuitable for CMP or even standard reflow techniques because shear forces can destroy these types of features. Also, many MEMS require unusual (for semiconductors) materials that have more in common with BCB than with SiO2. Planarization of these structures and materials is perhaps more difficult than that of standard semiconductor structures and materials.
Conclusion
This process holds the promise for truly pattern-density-independent planarization. In this initial feasibility study of press planarization, the results indicate the capability to provide both local and global planarization. In addition, on some of the most difficult structures that show large pattern density effects for CMP processing, the press planarization process shows little pattern density effect [2]. Results, however, are limited in scope and require significant further development before they can be applied commercially.
James E. Lamb III, Mark Daffron, Russell Hopper, Marci Whittaker, Sharon Scott, Brewer Science Inc., Rolla, Missouri
Acknowledgment
The authors thank Charles J. Neef of Brewer Science Inc. for providing the BARC material used in the planarization experiment.
References
- SKW Associates, www.testwafer.com.
- Dale Hetherington, "CMP: Future Needs and New Applications," Planarization for ULSI Multilevel Interconnect., Short Course, Santa Clara, CA, March 2001.
For more information, contact Russell Hopper, 2401 Brewer Dr., Rolla, MO 65401; ph 573/364-0300, fax 573/426-5321, [email protected].