Signs of progress with packaging Cu low-k chips

09/01/2003

The industry-wide struggles to integrate copper low-k processes with the rest of the semiconductor manufacturing flow have been thoroughly documented [1]. Much of the difficulty with the new materials has related to physical stress imparted by standard packaging processes. The low-k candidate materials' weak structure, typically due to porosity, has proven to be a roadblock to the proliferation of copper low-k technology [2]. Material issues relating to bonding to copper have also appeared.

Low-k advances

Although progress has been slower than hoped by the industry, there have been numerous recent announcements of advances and plans on the low-k front. Novellus Systems, for example, has claimed a breakthrough with a new deposition technology that allows dielectrics with k as low as 1.7. The material has "structured" pores that result in improved hardness as well as a dielectric constant below what many expected to be the limit for chemical vapor deposition (CVD) processes.

A recent announcement from Applied Materials follows a more continuous path from current CVD processes, extending its "Black Diamond" process to the 45nm node. The k value being targeted there is 2.4, but with the stack of layers used to improve the strength of the structure, the effective k will be 2.6.

Dow Chemical also recently announced a new variation on its SiLK low-k material. "SiLK D" is the latest in the family of spin-on materials, and it is designed to have a more controlled coefficient of thermal expansion profile. Dow Chemical's SiLKnet Alliance is also working on a hybrid structure that uses CVD and spin-on materials at different positions in an interconnect stack-up.

So there are still numerous low-k solutions in the marketplace, and compatibility with packaging processes is seen as a key feature for a successful solution. Dean Freeman, principal analyst at Gartner Dataquest, has said [3], "It appears that the final film decision comes down to the ability of each firm to integrate the material into its specific process and packaging flow."

Click here to enlarge image

null

Packaging developments

Along with advances in copper low-k wafer processing, the associated packaging technology has also moved forward in 2003. Some of the key developments have involved joint efforts between IC makers and packaging providers. For example, in April, Advanced Semiconductor Engineering (ASE), one of the leading packaging and test subcontractors, announced that it worked closely with Taiwan Semiconductor Manufacturing Co. (TSMC) to qualify ASE's wire bond and flip-chip ball grid array technology for use with TSMC's copper low-k process technology. This development was unusual because it involved the interactions of specific packaging and wafer technologies, reflecting increasing need for joint efforts in this arena. Amkor, the largest packaging subcontractor, made a similar announcement in July about packages developed for TSMC's low-k chips.

A technology introduction from LSI Logic demonstrated the same targeted approach for package technology development. An advanced flip-chip packaging process was created specifically for its 110nm copper low-k process for system-on-chip designs. According to Maniam Alagaratnam, VP of packaging development at LSI Logic, "Teams of engineers spent several months characterizing the materials and processes required to ensure the performance and reliability of our flip-chip packaging technology for SoC designs using LSI Logic silicon technology."

Flip-chip processing, such as that developed by ASE and LSI Logic, presents challenges that are not present in wire-bonded units. There is not the stress incurred during the wire-bonding process, but the physical coupling of the silicon and the package with flip-chip connections puts an ongoing stress on interconnect layers below the bond pads.

IMEC, the Belgian research group, has studied flip-chip low-k stresses and described a redistribution approach that increases the bond pad pitch, which reduces the stress at each connection [4]. The dielectric material in the redistribution layer is BCB with k = 2.7 and copper conductors. Because of the larger dimensions, the resistance of the interconnect in these distribution layers is much less than the resistance of conductors in the chip, so advantages in power and ground distribution can be realized if some of the interconnect is designed into those layers rather than the chip. IMEC has also developed processes that allow passive components to be embedded in the redistribution layer.

Bonding to copper

One of the mechanical issues with low-k dielectric materials is that they provide a more compliant surface over which wire bonding must occur. Wire bonding has been developed for decades with a hard SiO2 layer under bond pads, so new processes and material sets are needed to allow wire bonding to be effective and reliable with the new wafer technologies. Harder layers within the dielectric stack improve bondability, but research at the Institute of Microelectronics (IME) in Singapore has also shown the benefit of a cap metallization structure consisting of electroless nickel and immersion gold [5]. IME used test vehicles (see figure) designed specifically for these evaluations.

Test structure used by IME to evaluate a cap metallization structure of Ni and Au on top of Cu/low-k wafers. (Courtesy of IME [5])Click here to enlarge image

null

George Harman, the career-long wire- bonding expert at the National Institute of Standards and Technology, has studied material effects of bonding to copper surfaces [6]. A bare copper surface oxidizes, which significantly reduces bondability, but standard plasma cleaning is not enough to create a bondable surface on copper [4]. Metals such as Au, Al, Ag, and Pd can be used to create a bondable surface, and barrier layers (e.g., Ni) or plating solution additives can be used to inhibit copper diffusion through the cap layer.

Organic solderability preservatives have also been used rather than additional metal layers on top of copper, but according to Harman, "Results thus far have not been encouraging." A third option is a thin inorganic film, such as SiO2, SiN, Al2O3, or SiC. Such films can be applied with standard wafer processes, and if they are thin enough (<5nm), the wire-bonding process simply shatters the film to bond to the protected copper below it.

Evaluation tools

As shown in the table, the ITRS has identified a new challenge in defining methods for evaluating material behavior in copper low-k interconnects. Researchers at the University of Texas at Austin have used Moiré interferometry in combination with finite element analysis (FEA) to understand crack propagation at interfaces in low-k structures [7]. The energy release rate (ERR) at interfaces was identified as a key factor in delamination at interfaces, and the analysis showed that the ERR changes significantly after the packaging process. The Moiré interferometer was used to measure stress and strain of the packaged part, so that the FEA results could be verified. One interesting result is that interfaces parallel to the die surface are more sensitive to the stress of packaging processes than perpendicular interfaces.

Motorola has also done FEA of low-k structures and flip-chip packaging [8]. That effort defined the "J-integral," a function of strain energy density, as the crack driving force. This quantity is evaluated at different interfaces in the structure, and this work shows the benefits of using SiO2 as the top dielectric layer, since that is where the highest stress levels are generated. The effective k of the dielectric stack suffers only a modest increase in k with the single layer of SiO2.

An important part of any FEA work is having accurate material properties as input into the model, and Philips Research Labs has demonstrated a nano-indenter that evaluates the visco-elastic properties of low-k films under different process conditions [9].

All of this work shows that a serious R&D effort has continued to drive progress in reliable packaging of ICs fabricated with the latest copper low-k processes. Solutions have been introduced by leading providers of packaging technologies, and research reveals the fundamental behavior of copper low-k structures under packaging process stress.

References:

1. N. Hendricks, SST, pp. 31–32, March 2003.
2. Int'l Technol. Roadmap for Semiconductors 2002 Update, SIA, San Jose, CA, p. 100.
3. D. Vogler, WaferNews, p. 1, June 16, 2003.
4. E. Beyne, Proc. of the 2003 Int'l ITC.
5. V.P. Ganesh, et al., Proc.of the 2003 Int'l Conference on Electronics Packaging, pp. 138–143.
6. G.G. Harman, C.E. Johnson, IEEE Transactions on Components and Packaging Technologies, Vol. 25, No. 4, pp. 677–683, Dec. 2002.
7. G. Wang, et al., Proc. of the 2003 Electronic Components and Technology Conference, pp. 727–730.
8. L.L. Mercado, et al., ibid., pp. 1784–1790.
9. J. den Tooner, et al., ibid., pp. 708–712.

For more information, contact Jeffrey C. Demmin, at Tessera Technologies Inc., 3099 Orchard Dr., San Jose, CA 95134; ph 408/383-3691, [email protected].