Yield enhancement from wafer backside inspection
09/01/2003
Overview
While defects have always been a concern in wafer processing, until recently little attention has focused on backside defects, simply due to the lack of suitable methods and little awareness about effects. Now, using newly facilitated backside inspection technology and rigorous case studies, fab engineers have documented how backside defects can affect yield, scrap, and production costs.
Backside defects have been largely ignored for several reasons, including the lack of suitable equipment and methods for backside inspection and the lack of awareness about the impact of backside defects on semiconductor manufacturing, particularly on yield [1–4]; yield improvement was never directly correlated to backside defect reduction in any of these references.
Using a new defect detection technique, we set out to establish that the variety of backside defects can have a major impact on yield and scrap and ultimately production costs. We studied general particles and residues, "fall-on" particles that shed from the backside of post-processed wafers and land on a wafer below, and "sticky" particles that only migrate if physically contacted.
We hypothesized that all these defects would cause either yield loss or wafer scrap, and, if they could be minimized, a cost savings was possible through the elimination of clean steps, and a reduction in maintenance and parts replacements. Our data collection and analysis work is described in case studies below conducted at Agere's OR2 fab in Orlando, FL — a 200mm CMOS line.
Backside inspection methods
In the past, available techniques for backside inspection were destructive and therefore expensive. Several references discuss using inspection tools to map backside defects by loading a bare silicon wafer frontside down in a process tool and then scanning the frontside in an inspection system to get a measure of the backside defect density [1, 2, 3, 5]. Subsequent chemical analysis was conducted using different techniques (e.g., VPD-ICP, TXRF, etc. [1, 3]) limited to wafer-level contamination information, with some even limited to certain types of metallic contamination.
 Figure 1. Backside defect (>0.35µm) maps from three metal deposition tools. |
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This "manual flipping" method of backside inspection has numerous limitations: damage to the wafer's frontside, precluding wafer reuse, lack of corresponding process-side defect data, and lack of subsequent yield data for spatial correlation with backside data. Also, two wafers need to be run through a process tool to quantify both frontside and backside defects.
Engineers at KLA-Tencor have developed a backside wafer inspection enhancement — the Backside Inspection Module (BSIM) — for the SP1 laser-based monitor wafer inspection tool. With the wafer-edge-handling capability of the SP1 BSIM, one can now do nondestructive frontside and backside inspection of the same wafer. Since the method is nondestructive, both test and product wafers can be inspected. As a result, backside defects can be correlated to product yield data, monitor wafers can be reused, and both frontside and backside defect information can be gathered from a single wafer.
Arcing in metal deposition
Frontside particle measurements are a routine part of qualifying process tools for production. At Agere, we have discovered that backside particle measurements should also be required to qualify certain tools. For example, backside defects on a metal deposition tool have been known to be the catalyst for micro-arcing because particles form a space between the wafer and heater pedestal; micro-arcing can result in wafer fracture. Depending on the amount of damage, subsequent wafers may also fracture and the heater pedestal may need replacement. By controlling backside defects and their accumulation on the heater pedestal, micro-arcing can be minimized.
We collected backside particle data on three metal deposition systems to learn how particles accumulate on the heater pedestal: Tool 1 was new; Tool 2 had been in production for one month; and Tool 3 had run wafers for more than a year. We ran six monitor wafers frontside down in sequence on each tool.
While we expected the greatest accumulation of defects on Tool 3 due to its age, we observed similar defect counts on all three tools. The first wafer on each tool had a significantly larger number of defects that decreased with subsequent wafers (Fig. 1). The spatial signature of defects corresponds to the points of contact on the heater pedestal. Defect types, including scratches and surface particles composed of Al, Si, and O, were found on all three tools. The new tool also contained substantial metallic contamination, which makes sense since this tool had just been assembled. The downward trend in defect count demonstrates that running a monitor wafer face down effectively cleans the heater pedestal. While this method was not implemented on a periodic basis, it is recognized as a useful tool-recovery procedure.
We concluded that the best way to control arcing might be to inspect the backside of product wafers prior to deposition. A passive data collection study to correlate the size and position of defects to micro-arcing events would be necessary to establish an effective inspection.
Oxide deposition tool "season"
For Agere's oxide deposition tools, we suspected that backside particles caused by "season" (an oxide coating in the deposition chamber after in situ chamber cleaning) on the electrostatic chuck was affecting yield. Previous work had shown that post-processed wafers shed backside particles, and that some of these particles migrate to or fall on the frontside of the wafer below, ultimately resulting in "tungsten puddles," a yield-limiting defect. At the time of this study, a post-deposition wafer-cleaning step was in place to remove as many fall-on particles as possible. Pre- and post-clean inspections, with a SP1 BSIM, demonstrated that this clean removes most of the frontside fall-on particles and 69% of the remaining backside particles.
Despite the benefits realized by the clean step, there was still an opportunity to improve the process by further reducing post-deposition backside particles:
- The clean was not totally effective; not all "fall-ons" were removed and some remaining backside particles could still migrate to other wafers.
- The clean could be eliminated, resulting in lower cost and cycle time.
- The high backside particle counts tended to mask tool problems, making them difficult to troubleshoot.
- Backside particles caused helium-cooling leak-rate alarms, thus prohibiting a wafer from adequate electrostatic chucking, which causes excessive tool downtime and possible wafer scrap.
To attribute any high particle counts to the correct processing chamber and to interpret the results of this process optimization, we knew that it was important to distinguish frontside particles from fall-ons. We developed a new particle check procedure that allowed backside and frontside defects to be quantified separately: For a three-chamber deposition tool, we pre-scanned six wafers on an SP1 (cassette slots 1–6). Only the even wafers went into the process tool for deposition. The odd wafers remained in the cassette and acted as baffle wafers, blocking the post-processed wafer backside particles from falling onto the other processed wafers in the slots below. After processing, all wafers were post-scanned. The adders on the even wafers are a measure of frontside defects caused by the process, and the adders on the odd wafers are a measure of backside defects caused by the process, which results in fall-ons.
 Figure 2. Fall-on particle counts, as measured on baffle wafers, for three different season levels. Each level contains two months of daily process check data. |
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In this optimization study, we looked at different chamber season strategies labeled thick, thin, and none. While SIMS analysis has shown that a season effectively reduces wafer contamination from in situ cleaning gases and chamber wall material, these contaminants were found not to impact yield. Without any yield impact, we needed to consider not using a season to reduce costs.
We performed a long-term passive data collection study on the three season strategies, collecting frontside and backside particle data daily using an SP1.
The "no-season" experimental cell generated the least number of backside fall-ons by far (Fig. 2). Surprisingly, the "thick" cell generated notably fewer fall-ons than the "thin" cell. To verify this result, we conducted a similar experiment, in which backside defect counts were measured directly on the back of post-processed wafers. Four wafers were processed for each level with the same tool. The backside particle counts showed the same trend as the backside fall-ons in the passive data collection study.
We found that different seasoning levels did not significantly affect the frontside particle count, but a difference in defect types was observed. The no-season cell generated large embedded aluminum particles, whereas there was no evidence of these particles on cells with seasoning.
Since embedded particles have a greater yield impact than backside fall-ons, we have adopted the thick-season recipe. These studies verified the need to clean both the front- and backside wafer surfaces after oxide deposition.
These studies also demonstrated the need to monitor both backside and frontside particles. For this purpose, the SP1 BSIM offers two savings. First, by measuring the front and back of processed wafers, the same baffle wafers can be used to conduct process checks for the entire tool set. This saves 50% in control wafer use. Second, helium leak-rate errors could be reduced by monitoring incoming backside defect counts on product, thus reducing the probability of whole wafer scraps.
 Figure 3. Probe map showing yield impact from CMP hot spot. |
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Optimized in situ CMP clean
We have also used backside inspection to link a residue generated during CMP processing to the creation of hot spots (pattern defects from topography deviations in a wafer surface, caused either by a particle on a chuck or residue on the wafer backside). The residue spatially correlates to a small hole in the center of the CMP platen (Fig. 3). This defect occurred on two or more wafers on ~10% of all lots.
We applied different types of cleans after the CMP process and evaluated their efficacy in removing this residue. None were successful; we concluded that this defect could not be removed once the slurry had dried. Our alternate approach addressed optimizing the CMP in situ clean. This was successful in eliminating the residue and the associated hot spot defects. In this case, the SP1 BSIM was useful for evaluating different clean options. A backside inspection of monitor wafers used in the current daily process check may be appropriate to check for a degradation in the effectiveness of this clean and any other changes affecting the wafer backside.
An ongoing need
Once certain backside defect issues are resolved, other backside issues resulting in yield loss may occur. Frontside inspection programs involving both product and monitor wafers are well established to monitor for tool stability. However, backside defects offer a unique view of tool stability. For additional processes, characterization work is necessary to link backside defects to yield and scrap, and to determine the backside signature indicative of a tool problem.
The evolution to larger wafers, smaller design rules, and double-sided polished (DSP) wafers are three factors that will continue to increase the importance of understanding backside defect contamination on yield. In the case of smaller design rules, smaller particles are capable of causing electrical failures. In the case of DSP, there is speculation in the industry that eliminating the nooks and crannies of a rough backside finish means there are no hiding places for small particles when a wafer is chucked to a stepper's stage. The DSP process, therefore, may leave the lithography process more susceptible to hot spots then ever before.
Acknowledgments
The authors thank William Bevers, Joseph Buckfeller, Steven Lippy, Charles Storey, Jennifer Pope, Fred Weck, and Shane Wood of Agere Systems, as well as Blaine Anderson of Applied Materials for help with experiments. We also thank Ray Campbell, Christine Cauble, Todd Henry, and Shawn MacNish of KLA-Tencor for assistance with the SP1 and the SP1 BSIM.
Lesley A. Cheema, Leonard J. Olmer, Oliver D. Patterson, Agere Systems, Orlando, Florida
Susan S. Lopez, Mark B. Burns, KLA-Tencor Corp., San Jose, California
References
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- W. Au, et al., Proc. of ASMC, pp. 294–297, 1998.
Lesley Cheema is a member of the technical staff at Agere Systems, 9333 S. John Young Pkwy., Orlando, FL 32819; ph 407/767-7933, e-mail [email protected].
Leonard Olmer is a consulting member of the technical staff at Agere Systems.
Oliver Patterson is a member of the technical staff at Agere Systems.
Susan Lopez is a product-marketing manager at KLA-Tencor Corp.
Mark Burns is a regional product manager at KLA-Tencor Corp.