Exploring the link between nanotechnology and metrology
09/01/2003
Overview
Today we are seeing conventional IC technology approaching some fundamental limits while intriguing nanotechnology is just emerging in laboratories. It is entirely possible that the latter holds some keys to extending much needed device capability for end-of-the-roadmap needs, as well as for filling eventual metrology needs for nanotechnology fabrication itself.
The future of microelectronics and nanotechnology are intimately tied together. The smallest feature sizes on today's ICs are already falling below 50nm. The International Technology Roadmap for Semiconductors projects that in 15 years the smallest feature size will be <10nm [1]. If the industry is going to manufacture rapidly decreasing feature sizes at high volume during the next 15 years, then the research into nanotechnology deserves our attention today.
A sampling of research about nanotechnology illustrates potential links between nanotechnology and metrology. We need to compare the most advanced transistor devices and nanoelectronics to see if there are potential metrology applications for nanotechnology.
Fabricating nanotransistors
Recent work by Bruce Doris and co-workers at IBM has demonstrated transistor operation down to 6nm gate lengths [2]; these transistors are truly created by nanotechnology. They were fabricated on silicon-on-insulator (SOI) substrates with nano-sized silicon channel thicknesses <8nm. They describe 14nm gate-length transistors with a gate dielectric thickness (equivalent oxide thickness) of 1.2nm and the SOI silicon channel thickness of 4.6nm. This transistor has a saturation drive current of 439µA/µm at a Vdd of 1.5V.
When gate lengths shrink, the drive current/micron normally increases. When we examine the nanoworld, the first goal is to make a working device. As a figure of merit for this nanoworld, the cited work [2] indicates that 6nm transistors function and have a drive current of 130µA/µm at a Vdd of 1.5V. In other words, the transistors work; they turn off and on (Fig. 1).
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Are these transistors very different from today's CMOS? Yes, raised source-and-drain structures along with SOI substrates make this structure different from today's CMOS (Fig. 2). In these devices, the channel region could be considered a nanowire with the current flowing across its smallest dimension. In fact, one can refer to work at these dimensions as nano-CMOS.
 Figure 2. Schematic differences between a) traditional CMOS and b) the fabricated transistor structures of Bruce Doris [2]. |
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Nanotechnology
Molecular electronics, nanotubes, nanowires, and nanoparticles, as well as spintronics have all captured our attention recently. Each of these areas is an interesting branch of research.
Molecular electronics typically refers to the replacement of transistors with molecular switches. Molecular switches are typically two-terminal devices, while transistors are three-terminal devices. Thus, transistors have gain while molecular two-terminal switches dissipate power.
James Heath, Fraser Stoddart, and Anthony Pease at UCLA have demonstrated the use of catenanes or rotaxanes as molecular switches [3]. Catenanes are mechanically interlocking molecules that exhibit different positions relative to each other based on their oxidation state. The catenanes are attached between a tiled set of wires that forms the circuitry. Different conformations of these molecules have very different tunneling currents. A molecular switch made with {2}- rotane 54+ was reported to pass several nanoamps in the open configuration [3].
New metrology problems arise when new technology is invented. For example, the electrical properties of these new molecular switches require nontraditional testing. Although existing microscopy capability provides a view of the switching process, details of the organic structure are beyond present capability.
 Figure 3. A nanowire transistor is shown schematically. Current flows down the confined path formed by the nanowire. (Adapted from [4]) |
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Nanotube and nanowire transistors have been shown to have excellent operating characteristics. Sub-10nm-dia. semiconductor nanowires can be grown using catalyst particles and appropriate reaction conditions. Coaxial structures can be grown by depositing on top of the core nanowire. Charles Lieber at Harvard has even shown that the multishell wire fabrication method can be used to fabricate a coaxial FET with a Ge gate and a silicon oxide gate dielectric as outer shells [4]. The structure is p-Si core/i-Ge/SiOx/p-Ge, where the active channel is the i-Ge shell (Fig. 3). The gate length in this device is ~1500nm. The current for a gate voltage of 1 is between 1000 and 5000nA giving a figure of merit, the saturation current, in the range of 1µA/µm. This first nanowire transistor is quite an accomplishment.
The smallest transistor described above has saturation current ~100¥ greater. The current flows down the length of the nanowire, and not across the smallest dimension. This is in contrast to nanotransistors described above, where current flows across the smallest dimension. The distinction is significant because the effect of quantum confinement on conductance has been thoroughly discussed when the current flows down the length of a very thin (<130 atoms in the cross section) wire. The diameter of the nanowire is controlled by the size of the catalyst particle. In the case of coaxial nanowire transistor structures, the core wire diameter is set by the nanoparticle catalyst diameter.
Avoris and coworkers at IBM have demonstrated the electrical operation of carbon nanotube transistors [5]. Again, current flows along the length of the nanotube. The saturation current of their 260nm gate-length (CD) nanotube transistor seems to be similar to the nanowire transistor. The electrical properties for both nanotube and nanowire transistors are impressive considering that these results are the first examples of nanotechnology transistors. Carbon nanotubes can be fabricated with a number of different properties form insulating to conducting.
Addressing metrology
Today, feature dimensions already result in changes in materials properties [6]. The optical properties of very thin films used in transistor gate dielectrics are slightly different from those observed in bulk materials. As feature sizes shrink, property changes are expected to have a greater impact on device performance and on metrology. Furthermore, optical and other properties of ultra-thin SOI substrates used for nano-CMOS are known to be different from those of bulk silicon.
There is a strong link between nano-CMOS and the remainder of nanotechnology. Semiconductor and metallic nanoparticles have also been fabricated. The optical properties of nanowires and nanoparticles are different from bulk materials. The source of these changes is from quantum confinement and surface states. The dominant cause of property changes is still the subject of research. For example, the shift in absorption spectra for nanoparticles and nanowires can be calculated, but the true relative contributions of quantum confinement and surface states are unknown. Knowledge of the optical properties of ultra-thin films and structures is a critical part of developing useful metrology for their process control.
Metrology and characterization needs for nanotechnology and nanoelectronics have many similarities. The difficulties in observing the ultra-thin dielectric layer in a nanowire transistor illustrates the need for continued development of microscopy capability for characterization of both nanoelectronics and nanotechnology.
Development and application of advanced transmission electron microscopy will continue to be a critical part of materials characterization [6]. New methods, such as local electrode atom probe (LEAP), are being investigated. LEAP has the potential of mapping atomic positions in 3-D (Fig. 4).
 Figure 4. Atom-by-atom map produced by LEAP. (Courtesy Tom Kelly) |
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Microscopy is a critical part of materials characterization and in-line metrology. Eventually, nano-CMOS and possibly other forms of nanoelectronics will be manufactured at high volume. Then, some form of CD process control will be necessary. Whether that is a CD-SEM or something else is a topic previously discussed in this series [7].
Nanotechnology provides the exciting possibility of testing metrology with nanofeatures long before these feature sizes are available from advanced lithography [6]. Electron-beam lithography can be used to fabricate some nanofeatures. The biggest drawback is the need for controlling micro-roughness. Sidewall roughness can come from both printing in resist and etching these features. Despite this issue, electron-beam lithography offers the important ability to select feature shapes.
New lithography methods, such as imprint, offer other approaches. In this method, the mask has the desired pattern etched into it. As the mask is stepped across the wafer surface, it is filled with a polymer and flashed with a light source that solidifies the polymer. As the mask moves away from the wafer, the solid features are left behind. As with traditional optical lithography, etching produces the final feature shapes in the material below the solidified polymer. Another approach is direct fabrication of specific features. The above discussion can also be extended to new test structures for defect detection. Imagine having a series of high-aspect-ratio structures with ever-decreasing diameters that extend down to 10nm.
Conclusion
The world of nanotechnology provides many exciting opportunities for the semiconductor industry, including the metrology community. The first steps in exploring these opportunities are developing an understanding of the properties of nanotechnology. From an initial comparison between the most advanced transistors and transistors made using nanotechnology — exploring nanotubes, nanowires, and molecular electronics — it becomes apparent that there is a need for advanced materials characterization. It is also apparent that there is potential for using nanotechnology to fabricate nanofeatures to evaluate and advance measurement technology.
Alain C. Diebold, International Sematech, Austin, Texas
Acknowledgments
I gratefully acknowledge discussions with Bruce Doris, Genadi Berseker, and Peter Zeitzoff.
References
International Technology Roadmap for Semiconductors, SIA.
- B. Doris, et al., Technical Digest of the 2002 International Electron Devices Meeting, IEDM, pp. 267–270, 2002.
- A.R. Pease, et al., Acc. Chem. Res., 34, pp. 433–444, 2001.
- L.J. Lauhon, et al., Nature, 420, p. 57, 2002.
- S.J. Wind, et al., Appl. Phys. Lett., 80, 3817, 2002.
- A.C. Diebold, Proceedings of the 2003 International Conference on Characterization and Metrology for ULSI Technology, Austin, March 24–28, 2003, to be published in late 2003.
- A.C. Diebold, D. Joy, Solid State Technology, pp. 63–70, July 2003.
Alain Diebold received his PhD from Purdue U. He is a senior fellow at International Sematech, 2706 Montopolis Dr., Austin, TX 78741; ph 512/345-7680, e-mail [email protected].