Technology News
08/01/2003
Angstron Systems shows full-wafer (300mm) data on Cu ALD
In Solid State Technology's "ALD Special Report: Where's the metal?" (Jan. 2003), industry experts debated the merits and problems associated with Cu ALD and TaN ALD. It is clear that the ALD process, while achieving highly conformal films, comes with challenges when metal is being deposited versus a dielectric. Start-up company Angstron Systems Inc., Santa Clara, CA, has data showing full-wafer (300mm) copper nucleation directly on TaN ALD.
Company founder and president Tony Chiang explains that one key to the company's Cu ALD process is the very low temperature at which it is done — at temperatures much less than (~3×) conventional ALD processes while achieving a deposition rate of 3–4Å/cycle.
When it comes to depositing thin copper films, "The higher the temperature, the greater the degree of copper agglomeration," explains Chiang. "Also, chemisorbed precursor molecules tend to decompose the higher the deposition temperature."
Because the chemisorption of the source precursor is incomplete in most ALD processes, only a sub-monolayer/cycle deposition is achieved. "By using a very low temperature, saturative chemisorption can more easily take place without decomposition," notes Chiang. He adds that simply running at low temperatures does not guarantee saturative chemisorption, hence the company also uses a controlled chemisorption technique.
Saturative chemisorption in turn enables high-density metal films, which are lower in resistivity. Generally, one would want as thin a barrier layer with as low a resistivity as possible for faster interconnects. "Working with such a low resistivity film allows a broader range of barrier thicknesses," states Chiang.
The company also released step coverage results for TaN ALD barrier layers (Figs. 1–3). "It's important to achieve thickness uniformity of the Cu layer across the wafer, but film property uniformity of the barrier layer must also be maintained," says Chiang. "Even if the thickness of the barrier is uniform, if the resistivity varies significantly, it may cause significant variations in line and via resistance of the interconnect. This effect is enhanced if the barrier resistivity is high since it contributes more to the overall interconnect resistance."
 Figure 1. TEM step coverage of TaN ALD within a <0.07µm, >15:1 A/R trench. Source: Angstron Systems Inc. |
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 Figure 2. TEM step coverage of TaN ALD within a <0.1µm, >12:1 A/R via. Source: Angstron Systems Inc. |
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 Figure 3. SEM of integrated TaN ALD/Cu ALD stack in HAR trenches. Source: Angstron Systems Inc. |
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300mm wet processing tool in place for boom
The marketing logic behind the recent introduction of a high-throughput single-wafer clean platform by SEZ, Villach, Austria, points to rising use of single-wafer wet surface prep at the expense of wet benches and spray (see figure), all driven by 300mm processing needs.
While SEZ only owns 12% of the wet surface prep market, its views to the future are likely significant because more than 80% of all single-wafer tools installed today are made by SEZ and 40% of its tools delivered in 2002 were for 300mm.
The new tool platform — the Da Vinci series, a robotic multichamber application of SEZ's proven process chemistry capabilities — was designed to help the industry transition from batch processing to 300mm single-wafer cleaning technology. The first application targeted with Da Vinci is BEOL polymer cleaning using parallel chambers for processing up to eight 300mm wafers simultaneously.
Reportedly, the platform offers "the highest throughput (~200 wafers/hr) and smallest footprint currently available in a single-wafer approach. We have specifically targeted BEOL processing of 300mm wafers with 90nm and below geometries. This capability is being evaluated in Asia where the system is needed to replace competitive tools that cannot deliver the reliability these customers demand," says Jim Mello, executive VP at SEZ Group.
Mello emphasizes that tools like this are extremely important to have in place right now; even though the industry is still down, the future holds a lot of opportunity surrounding 300mm. "The market data show that 80% of the spending into 2004 is going to be for 130 and 90nm technology. In addition, $18 billion worth of new 300mm fab projects are slated to start in 2003," he says. According to SEZ's market data behind the launch of Da Vinci, there are 35 fab projects — new plants, upgrades, and expansions — expected from now until the middle of 2004. "Just about all of these will be 300mm. In the next four quarters, as many as 10 new 300mm wafer fabs will begin production," says Mello.
SEZ estimates that single-wafer systems currently address up to 40% of the available market for BEOL cleaning.
 The impending market evolution of wet surface preparation to single-wafer tools. Courtesy: SEZ |
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"Shrinking design rules and new materials like copper and low-k dielectrics, together with their stringent processing requirements, are driving an increase in demand for single-wafer solutions. This is particularly true for volume chipmakers and foundries producing high-aspect-ratio geometries at the 90nm node and below, since batch technologies cannot effectively clean high-aspect-ratio structures as well as single-wafer systems can," says Mello. "Single-wafer cleaning technology also enables faster cycle times and an increased flexibility in lot scheduling, reducing work in progress."
Mello notes, "In developing the Da Vinci series, we worked closely with our customers to ensure that we would meet their most advanced technology and time-to-market requirements. As customers continue to delve into 90nm geometries and below, they're looking for greater efficiency and yield-cost savings than ever before. Not only do they need high-performance, high-volume processing solutions to remove etch residues when fabricating advanced devices, but they also require an upgrade path for future technology and process improvements."
SEZ has defined a roadmap to move the Da Vinci platform into FEOL cleaning, including double-sided cleaning. — P.B.
Step-and-flash imprint lithography: Can it fit the bill for NGL?
IC manufacturers don't need much practice to shake their heads in disbelief. The out-of-sight price tags of some next-generation lithography (NGL) tools have been hinted at for quite some time; some sources say NGL tools will be priced ≥$50M. But one NGL candidate — nanoimprint lithography — appears to be gaining ground.
Evidence of nanoimprint lithography's growing importance could be seen at last year's First International Conference on Nanoimprint Nanoprint Technology. Motorola's Doug Resnick and Dave Mancini followed up their presentations at that conference with more data on step-and-flash imprint lithography (SFIL) at this year's SPIE Microlithography Conference. SFIL is a variant of a micromolding process that uses a transparent template to transfer patterns to a substrate.
While emphasizing SFIL's low costs — no need for costly projection optics, sophisticated light sources, or resists — Resnick maintains that if overlay, defectivity issues, and template infrastructure issues can be resolved, it could be a real contender for NGL, even down to 10nm.
 CD uniformity on a template and CD uniformity on a printed wafer. Courtesy: Motorola Labs |
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The template infrastructure to support SFIL (i.e., write, inspect, and repair a 1× template) Resnick believes, is probably the biggest problem. "Our industry is presently only capable of doing this on 4× reduction masks," notes Resnick. "The switch to 1× is a big deal. Your e-beam tool must have good resolution, good image placement, and must be fast. Inspection may have to be done with e-beam-based tools." Repairing 1× templates will require additional development of either FIB, micromachining, or possibly other techniques.
Regarding the difficulties of switching to 1× templates, Mike Watts, VP of engineering at Molecular Imprints, believes that the change, while challenging, may not be completely out of the ordinary. "With existing 4× masks, by the time you add RET and OPC decorations, the resolution is about 1.5× for the finest features, rather than 4×," explains Watts. "So a 1× template is not as much of a stretch as it would seem."
Recent CD uniformity results obtained at Motorola Labs (see figure) were of a pattern that was written in an 8×8 array. The data are the results for 30nm features; for both the template and the printed wafer, nearly every data point fell within 3nm of the mean. The key to SFIL's potential lies in its resolution being limited only by the ability to form a relief image in the template used, according to Resnick.
Another indication that SFIL is making headway is the recent news (May 20) that Motorola will receive an Imprio 100 tool set from Molecular Imprints Inc. (MII) to conduct additional research. The two companies have been working together for two years and the tool set is the first product offered by MII. The 100 version was launched in 2002 and was designed for use in development environments using 200mm wafers.
According to the company's business development manager, Mike Falcon, a follow-on toolset, the Imprio 300, is slated to have a throughput for production volumes (25wph) of 300mm wafers by 2005. An interim version to be launched in 2004, the Imprio 200, will have a throughput of 6wph for either 200 or 300mm wafers.