Developing sub-90nm low-k/Cu solutions
08/01/2003
By Keith Buchanan, Peter Sermon, Trikon Technologies, Newport, Wales
Paul Siblerud, Semitool Inc., Kalispell, Montana
The adoption of low-k materials into Cu damascene device structures has taken longer and required more work than anyone in the semiconductor industry had predicted. While materials with k = 2.8 are finally on the cusp of volume production, there is still work to be done on integrating k <2.5 films into Cu devices for use at the 65nm technology node and below. Such materials are typically porous and inherently weaker than their traditional counterparts, offering less resistance to chemical and mechanical degradation.
Resolving technical issues of the two most challenging aspects of low-k/Cu integration requires a working relationship between upstream and downstream process steps to implement both Cu and low-k. To this end, Trikon formed a process integration department, which has been collaborating with Semitool and other leading industry suppliers.
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The work with Semitool gives access to critical wet cleaning and Cu-electroplating technologies, which are key parts of the backend process flow used at Trikon (Table 1). The single-wafer surface preparation tooling allows for the evaluation and optimization of the post-ash, wet polymer cleaning process to ensure compatibility with the porous low-k Orion material (Table 2).
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The collaboration allows Semitool to evaluate different Cu-plating electrolytes through electrical testing of damascene interconnect test structures, investigating some of the key issues relating to the integration of porous low-k dielectrics in advanced interconnects.
Sub-90nm structures pose several challenges for the deposition of copper. Seed thickness along sidewalls is minimized in large part due to the aspect ratio, which increases resistance. This needs to be compensated by both electroplating hardware and chemistry. Copper fill is challenging if not impossible in <65nm structures with low acid chemistry and conventional plating techniques. A third issue is the mechanical integrity of the new ultra-low-k materials and the damaging effect of CMP. Minimizing the stresses on this material by attention to waveform during plating and overall uniformity control results in reducing overfill, and eliminates much of the CMP burden, resulting in a more robust process (see the figure).
Utilizing the Semitool reactor, it was possible to obtain consistent sub-65nm damascene plating with the integration of anneal, copper contamination control, and chemistry enhancement for production worthiness.
Acknowledgments
Orion, Planar P300, Omega, M0RI, C3M, and HiFill are trademarks or products of Trikon Technologies. Raider Clean and Raider ECD are trademarks of Semitool.
For more information, contact Keith Buchanan, process integration manager, Trikon Technologies, Ringland Way, Newport, South Wales, UK NP18 2TA, ph 44/0 1633 414025, fax 44/0 1633 414180, e-mail [email protected]; or Paul Siblerud, VP of marketing, Semitool Inc., 655 West Reserve Drive, Kalispell, MT 59901, ph 406/752-2107, fax 406/752-5522, e-mail [email protected].
Integrating MOCVD diffusion barriers with porous low-k dielectrics
To ensure sufficient conformality in damascene interconnect structures as feature sizes shrink, chipmakers will eventually move from PVD to CVD (metal organic and atomic layer) technologies for the deposition of the copper diffusion barrier. Prevention of the diffusion of CVD metal precursors and reaction products into porous dielectrics is a major integration challenge and demands that porous trench and via sidewalls be "sealed" before metal barrier deposition.
 Dark-field TEM image of a single damascene trench in Orion 2.2 porous low-k. |
While sealing can be achieved by the deposition of a thin, conformal and nonporous dielectric layer, this will increase the effective dielectric constant between the metal lines. A preferable approach is to use a plasma treatment to locally densify the sidewalls, which can be achieved through an additional process step after resist strip. Alternatively, the resist-stripping process itself can be optimized to leave the trench and via sidewalls sufficiently densified to prevent CVD barrier penetration. Any subsequent wet polymer-cleaning step must also be optimized to prevent etching of the densified layer.
The figure shows a dark-field TEM image of a single damascene trench in an Orion 2.2 porous low-k film. The 8nm thick MOCVD TiN(Si) Cu diffusion barrier is deposited over plasma-sealed sidewalls and the trench is filled with Semitool's electroplated Cu. The sharp interface suggests no gross diffusion of barrier material into the porous low-k. Elemental analysis of the TEM sample does not detect trace metal within the dielectric, showing the trench sidewalls have been successfully sealed.