The future of SOI and strained Si
08/01/2003
Solid State Technology asked IC manufacturers and a developer of strained silicon to comment on the roles of both strained silicon and SOI in future device technology.
SOI and strain: CMOS performance enhancers
By W.P. Maszara, senior member, technical staff,
Qi Xiang, senior member, technical staff,
Zoran Krivokapic, member, technical staff,
Ming-Ren Lin, AMD Fellow, Strategic Technology Group, AMD, Sunnyvale, California
High-performance logic CMOS devices can gain from performance enhancers such as strained channel or the partially/fully depleted architecture of transistors built in silicon-on-insulator (SOI) substrates. Both features can be incorporated into the CMOS device structure and can independently boost its performance.
Strain, appropriately applied to the device channel, can significantly increase (>50%) channel mobility, consequently increasing drive current by a sizable fraction of the mobility gain.
 W.P. Maszara |
SOI transistor architecture brings benefits, including reduced junction capacitance, which increases switching speed. A particular flavor of SOI transistor — fully depleted (FD SOI) — adds additional performance improvements: lower vertical field in the channel needed to switch the device (for higher mobility); further reduction of junction capacitance; and better scalability than bulk silicon devices. Overall, SOI devices have been shown to increase circuit performance and/or reduce active power consumption by ≥20%.
Implementation of SOI technology requires different, more expensive substrates than those for standard bulk silicon technology, however. Some modifications of process technology and circuit design are also needed when migrating to SOI. The added expenses are justified, and high-end microprocessors have been introduced to the market by IBM, Motorola, and AMD using partially depleted SOI technology (PD SOI). SOI devices are considered very scalable, with their architecture morphing from partially depleted SOI for the current generation to the fully depleted variety for future generations.
While SOI is a unique architecture choice for CMOS devices and requires deliberate efforts for its implementation, the strain is omnipresent in devices and one can realize its benefits or suffer from it unknowingly. Only now is the full benefit of strain engineering being realized.
Careful analysis of strain impact on channel mobility indicates that electrons and holes react differently to different spatial (3-D) components of strain. Tensile strain along the direction of electron current generally increases electron mobility, while hole mobility benefits from compressive strain. Two transverse components of strain also affect mobility.
Two integration approaches can be utilized to induce desirable strain in transistors: straining by device elements and strained substrates.
- Straining by device elements. Proper choice of materials and processes used for transistor elements has been shown to be capable of significantly straining the transistor channel and modulating the carrier mobility. This includes shallow trench isolation (STI), silicide contacts, spacers, overlayers, and gate electrode materials. All these components may be applied/modified selectively to n- and p-type devices for maximum benefit. An overlayer of SiN used as a contact etch-stop, for example, can be
selectively placed over NMOS in compressively-strained, and over PMOS
in tensile-strained form to impart tensile and compressive strain in
their respective channels. - Strained substrates. An alternative way of implementing strain in the transistor is to form the channel in an epitaxially grown Si film over a stack of epitaxial films, such as Si-Ge, with a lattice parameter of the top film slightly different from Si (usually larger). This approach amounts to a need for specialized substrates and requires major modifications to the device process design. Formation of strained-Si SOI substrates typically involves transfer of a relaxed Si-Ge layer or strained Si layer (or both) by wafer-bonding processes.
Whatever the source of strain in the channel, the amount of strain can be amplified by the proper choice of device layout — the length, width, and crystallographic orientation of the active silicon. The latter is due to the fact that elastic properties of silicon are highly anisotropic.
Scalability of performance benefits from various strain enhancers needs more study and those benefits may scale differently. Early data suggest that the benefit from Si-Ge diminishes with smaller dimensions, while other enhancers, such as STI or overlayer engineering, may increase its effectiveness in straining smaller transistors.
Both types of strain enhancers, the modular elements of the device, and the substrates, are in late developmental stages. The former are generally less expensive and easier to implement; most, if not all, can be utilized additively for increased performance. As in the case of SOI, the projected performance benefit from strain enhancers is expected to outweigh the cost of their implementation in high-performance products. Several companies are planning to introduce strain engineering in their logic technology in the near future.
The methods for introducing strain into CMOS devices can be applied in bulk as well as in SOI device technology. But SOI devices are expected to benefit more from the stressing media because the placement of a thin device silicon film on a more elastic, buried oxide film would make it more responsive to the applied straining force. Utilization of relaxed SiGe in the substrate for epitaxially grown channel Si films for PD SOI devices could be an exception here as there is a requirement to use a significantly thinner Si-Ge film in PD SOI than in bulk Si. In such cases, the straining efficiency of Si-Ge film may be somewhat less than in the bulk case. Future generations of SOI will likely employ FD SOI devices that require extremely thin device films, and if those were to rely on strain built into the substrate, the strained Si film alone would need to be formed (e.g., by wafer bonding), without Si-Ge, a concept yet to be clearly demonstrated.
For more information, contact Witek Maszara at [email protected].
Strained silicon and SOI: Complementary technologies
By Ken Rim, research staff member, T.J. Watson Research Center, IBM, Yorktown Heights, New York
Geometric scaling has enabled continued CMOS device performance enhancement as well as an exponential increase in circuit integration density. Physical limitations such as leakage current and power density, however, make geometric scaling an increasingly challenging task in deca-nano dimensions, impeding the pace of performance enhancements. This motivates the search for innovations, both in device structures and materials, which can extend CMOS device scaling and performance trends.
 Ken Rim |
SOI MOSFET provides advantages over bulk MOSFET devices in both circuit speed improvement and channel length scaling; IBM has been utilizing SOI in CMOS technology since 1999. Smaller junction capacitance, made possible by the presence of an insulating layer under the active silicon region, leads to a reduction of capacitive load in CMOS circuits and translates to faster circuit speed and/or reduced power consumption.
A newer idea that is receiving much attention in the industry is strained Si MOSFETs, recently demonstrated in modern CMOS integration by IBM and others. In strained Si MOSFETs, the current drive is improved in the channel made of a layer of strained Si, in which electron and hole transport is enhanced by changes in the electronic band structure of Si. Strained Si MOSFET is an innovation in material that enables CMOS performance improvement, whereas SOI MOSFET can be viewed as an innovation in device structure.
An exciting possibility is that the benefits of strained Si can be combined with those of SOI. In a SOI MOSFET with a strained Si channel, parasitic capacitance can be drastically reduced by the buried insulator, while the current drive of the device is enhanced by the strained Si channel. The principles that give rise to the advantages of strained Si and SOI structures are not expected to interfere with each other, since the innovations target two different regions of a MOSFET — buried insulator under the active region and the channel region itself.
In fact, strained Si and SOI can complement each other well to achieve maximum performance benefits. One example is in junction capacitance and leakage. In most cases, a strained Si channel is formed on a thick layer of SiGe. The source and drain junctions of a bulk strained Si MOSFET are thus formed within the SiGe layer, which has lower energy gap and higher dielectric constant, leading to higher junction capacitances and junction leakage. When a strained Si channel is formed in an SOI structure, the increased junction capacitance and leakage associated with SiGe can be reduced, mitigating the potential disadvantage of strained Si on SiGe.
The structures that place a strained Si channel layer on SOI have been reported by IBM and others. The demonstrated techniques involve epitaxial growth of SiGe followed by layer transfer or thermal treatment of the layers to create SiGe-on-insulator structures. A strained Si layer is then epitaxially grown on the SGOI before CMOS device fabrication.
For the past few decades, new materials and device structures have resulted in exponential growth of performance and integration density of silicon CMOS technology. One common condition for each innovation is that it was built on the advantages of existing ideas, without compromising them. Strained Si on SOI can be an innovation that extends the performance trend of SOI devices and enables further advancement of Si CMOS technology by adding to the advantages of SOI devices.
For more information, contact Ken Rim at [email protected].
Advanced materials: Driving enhanced performance
Mayank Bulsara, co-founder/CTO, AmberWave Systems, Salem, New Hampshire
 Mayank Bulsara |
Individually, strained silicon and silicon on insulator (SOI) represent important substrate engineering technologies that offer viable alternatives for semiconductor manufacturers looking for higher speed and lower power consumption. Combining these advances to create strained silicon-on-insulator (SSOI) transistor technology is feasible in the near future and will have the additive value of strained silicon's high-mobility carrier characteristics and SOI's reduced junction capacitance.
With SSOI, semiconductor manufacturers could potentially offset, delay, or enhance multiple generations of the multibillion dollar, high-risk, upfront capital expenditures that are typically required to stay at the cutting-edge of technology. This reinforces the fundamental impact that advanced materials are having, and will have, on the industry.
SSOI's potential has attracted a good deal of attention since its first demonstration in late 2002 (T.A. Langdo, et al., 2002 IEEE International SOI Conference, pp. 211–212). Manufacturers and designers are now taking paths for SSOI's commercialization very seriously. It is no coincidence that the first demonstration of SSOI material and the corresponding industry momentum come directly on the heels of the commercial acceptance of bulk strained silicon technology.
Looking at the earliest days of strained silicon R&D sheds light on today's questions about the feasibility of SSOI. At that time, questions centered on the ability to fabricate strained silicon substrates and transistors in any type of production environment. Even if the technology was manufacturable, there were concerns about whether the theoretical enhancements attainable with strained silicon could still be realized and considered substantial in state-of-the-art circuits. Today, the industry has accepted the commercial viability of strained silicon and the 30–40% circuit speed improvements made possible with strained silicon-based circuits at cutting-edge transistor dimensions (Q. Xiang, et al., First International SiGe Technology and Device Meeting, pp. 13–14, 2002).
SSOI faces questions similar, but subtly different, to those asked about strained silicon in its earliest days. Although some basic demonstration questions at the transistor integration level remain, the key individual components of SSOI substrate-manufacturing technology have already been validated. The key questions about SSOI are: 1) when can substrate technology be made available in commercial quantities, and 2) what are the economics of its deployment? To understand the basic thinking behind the answers, it is necessary to review the steps and the framework involved in fabricating SSOI substrates, while considering the stage of advances required at each step to make this a commercially viable product.
The first step in fabricating an SSOI substrate is obtaining a high-quality (material and surface), low-cost, bulk strained silicon wafer. While these wafers are commercially available, the resources for making them are largely tied up in the commercial ramp-up of bulk-strained silicon technology. So, while the economics of this first step are improving due to the sense of urgency surrounding current commercialization efforts, the tailoring of the technology for SSOI substrate fabrication will be slower in the near term.
Steps two and three, the implantation of an "atomic scalpel" species, typically hydrogen, and the wafer bonding and annealing for layer transfer and bond strengthening, require a new, specific development for SSOI. The infrastructure and economics, however, are well on their way to being commercially viable, because the steps are largely the same for making layer-transferred SOI technology.
The last step is the precise removal of the layer-transferred SiGe layer on top of the strained silicon film. This step is critical for determining the final thickness and uniformity of the strained silicon film, and it is the least demonstrated in terms of commercial viability. The first step, the fabrication of the bulk strained silicon wafer and the final step, the removal of the ancillary SiGe layer, are critical elements of SSOI technology and require an understanding of the behavior and processing of relaxed SiGe alloys.
The fast and economic deployment of the SiGe-based steps for SSOI technology largely rests on how quickly substrate-manufacturing organizations can infuse this knowledge into their state-of-the-art developments. As with the rest of the semiconductor industry, R&D budgets are at a premium, and business models for the deployment of such technology are going to most likely involve partnerships and licensing arrangements for the essential intellectual property. Once these issues have been addressed, the future is bright. It is now just a matter of raising awareness of the cost-performance benefits of this technology and securing its place on the roadmap.
For more information, contact Mayank Bulsara at [email protected].