Simplifying multiple V_T process flows using chained implants

08/01/2003

By L.M. Rubin, M.S. Ameen, Axcelis Technologies Inc., Beverly, Massachusetts

Overview

Below the 100nm node, it is impossible to simultaneously meet drive current and gate leakage specifications for leading-edge devices using SiO₂ or SiON gate dielectrics. This has forced the fabrication of multiple transistor designs in a circuit. Many 90nm processes contain up to three distinct NMOS and three distinct PMOS designs, each independently optimized for high speed or low power consumption. This requires up to six different well fabrications in the process, increasing implant requirements. Manufacturers address this challenge by chaining together all implant steps in the same well to reduce the WIP management burden and lot cycle time.

Transistors with multiple threshold adjust voltages (V_T) are being increasingly used in advanced logic circuits. Due to material limitations of traditional SiO₂-based gate dielectrics, many 130nm and 90nm process flows call for two or even three distinct NMOS V_T values, with a corresponding number of distinct PMOS transistors.

Leakage issues in ultrathin gate dielectrics force the dielectric to be made thicker than would otherwise be desirable from an electrical standpoint, resulting in reduced control of the transistor on-current (I_ON) and off-state-current (I_OFF) values. Among other effects, this makes it impossible to achieve optimum ION and IOFF simultaneously, regardless of the choice of transistor threshold voltage.

High values of V_T allow low I_OFF at the expense of low I_ON for circuit applications where power management is more important than speed. In contrast, a low V_T gives a high I_ON at the expense of high I_OFF for situations where speed is more important. Avoiding this compromise is a major motivation to replace the familiar SiO₂ with high-k gate dielectrics. Unfortunately, high-k materials pose significant integration challenges and are not expected to enter volume production until at least 2005. Most likely, there will still be multiple V_T circuits for optimum performance, even if high-k enters widespread use.

Chaining defined

Semiconductor manufacturers prefer to accommodate additional implant requirements by increasing implanter productivity rather than by acquiring additional implanters. Fortunately, most of the new implants required for multiple V_T processes are good candidates for implant chaining. A chain is defined as two or more separate implants completed without handling the wafers between implants. Separate implants are those requiring ion beam retuning between implantation steps because the ion species, energy, or both have changed.

If just the wafer orientation with respect to the beam is changed (e.g., in a quad implant), it is not an implant chain. Quad implants are usually implemented to optimize device performance, while chained implants are used primarily to improve manufacturing productivity. Quad implants can be combined with implant chains as necessary, however. Since implant chaining requires more frequent beam retuning than running a single implant on dozens of wafers, implant chaining can provide productivity improvements only if the beam-tuning time/wafer is sufficiently small. This is the major technical challenge in successfully implementing implant chains.

Counting implants

The total number of implant steps in a typical CMOS logic process has been steadily increasing with each new technology node (see table). Primarily because of the proliferation of multiple transistor V_T values, this long-term trend is somewhat accelerated for the 130nm and 90nm nodes. Whereas many 180nm processes have a single NMOS V_T and a single PMOS V_T, a typical 90nm process has three V_T values for each device type.

Figure 1. Three NMOS transistors with identical well implants but distinct VT adjust implants.Click here to enlarge image

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To fabricate three transistors with different V_T values, three separate masks are necessary for the V_T adjust implants (Fig. 1). All transistors can be implanted simultaneously if the other well implants are common to each, but this requires a fourth mask that opens over all three transistors but not those of the opposite type. Since a masking step costs far more than an implant step, it makes economic sense to repeat identical well implants rather than add an additional mask solely to reduce the implant count. From an implant standpoint, a 90nm process effectively has six distinct transistor types, instead of the two types (NMOS and PMOS) of earlier processes. Since a retrograde well consists of 2–3 implants (including V_T adjust), this increases the total number of well implants from 4–6 to 12–18.

Click here to enlarge image

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Impact on productivity

Chaining clearly cannot be implemented unless the process flow calls for all the implants in the chain to go into the same photoresist mask. Traditionally, each implant was a separate step in the process flow, and wafers were queued up in between. This strategy is undesirable from a cycle time perspective, since queuing can often be the longest part of an implant sequence. Modern multiwafer implanters are designed to tune quickly in order to implement chains efficiently (Fig. 2). On a multiwafer implanter, each lot experiences only one queue step/chain, regardless of the number of implants in the chain. The loading, tuning, and implant steps after the chain are performed twice for a 25-wafer lot (since the batch size is 13 wafers), but with no extra queuing steps. This is essential to improving factory-level productivity.

Figure 2. Implant sequence for a three-implant retrograde well, both with and without chaining. All times, except for queuing, are based on actual state-of-the-art multiwafer and single-wafer implanters processing 300mm wafers.Click here to enlarge image

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In contrast, chaining on a single-wafer implanter is prohibitively slow because the beam-retuning time is amortized over only one wafer vs. 13 in a multiwafer implanter. Implanting a well on a single-wafer implanter therefore requires scheduling each implant as a separate step, with an associated queue time. The cycle time advantage of chaining thus increases as the number of implants in the chain increases. Additionally, the reduction in load/unload steps made possible by chaining will reduce the number of handling-related particles deposited on the wafers.

Queue time (defined as the time between wafers' completing processing at a given tool and being delivered for processing at the next tool) is difficult to quantify, but is known to be highly variable within a fab. By reducing the number of queue steps, chaining not only provides faster cycle times but also reduces the variability in the work-in-progress (WIP) flow in the fab. Figure 3 shows the net throughput (wafers out/hour, with all implants completed) for a chain of three implants with and without chaining as a function of the average queue time.

Figure 3. Throughput for three implants as a function of queue time. All other implant process times are fixed as shown in Fig. 2. The throughput advantage of chaining increases steadily with increasing queue time.Click here to enlarge image

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For chains of >3 implants, the throughput advantage of chaining will be even greater because of the elimination of extra queuing steps. An additional consideration is the performance enhancement of chained processes within high-volume automated 300mm fabs. For systems featuring multilevel, interbay automated FOUP delivery, each process-pass through the machinery places a burden on the system [1]. Chaining can significantly improve the efficiency of the bay and eases overall WIP management, as fewer steps needed result in fewer moves by the transfer system. For fully automated machine-to-machine processing, it becomes cost-prohibitive not to chain wherever possible. Consequently, chaining is gaining acceptance in advanced semiconductor processing.

Conclusion

The demands of advanced circuits and the material limitations of conventional gate dielectrics have resulted in process flows with many more threshold voltage values. This greatly increases the total implant count and the opportunities to implement implant chaining. Chaining makes up to four implants appear as a single step at the factory level, greatly reducing wafer transport requirements and WIP burden. Chaining reduces total cycle time and often offers significant productivity and throughput advantages. It is a relatively straightforward process qualification to introduce chains into an existing, lower-throughput, single-wafer approach.

Acknowledgments

The authors thank Tom Parrill and Bill Chang of Axcelis for helpful suggestions.

Reference

1. B. Sohn, "Overview of Semiconductor Manufacturing," Technical Short Course, presented at IEDM 2002.

Leonard M. Rubin is senior scientist at Axcelis Technologies Inc., 108 Cherry Hill Dr., Beverly, MA 01915; ph 978/787-4257, fax 978/787-4050, [email protected].

Michael S. Ameen is process technology manager at Axcelis Technologies Inc.