Correcting HDP film thickness with a wet pre-planarization etch
08/01/2003
By Hayato Iwamoto, Hajime Ugajin, SONY Corp., Kanagawa, Japan
Kei Kinoshita, SEZ AG, Villach, Austria
Overview
Precise control of chemical mechanical planarization is becoming increasingly important, and uniformity is greatly influenced by the step and height of patterns. Optimization of dummy patterns helps to improve uniformity at the CMP step, but changes to the VLSI design are required [1–7]. A tailored wet pre-planarization chemical process can correct HDP film thickness uniformity and thereby minimize impact on CMP. A novel pre-planarization process for patterned wafers was developed and implemented to minimize dishing effects by compensating for film deposition nonuniformities.
Continuous shrinkage of IC device dimensions imposes stringent requirements for the formation of shallow trench isolation (STI) structures. Major challenges include void-free oxide deposition for higher-aspect-ratio trenches, and chemical mechanical planarization (CMP) of these structures to remove excess oxide with a high planarity and uniformity. High-density plasma chemical vapor deposition oxide (HDP CVD SiO2) is one of the insulation choices that enable void-free trench formation via a high-quality film. Many times however, the films formed are nonuniform due to distortion of the film deposition by inhomogeneous distribution of plasma and gases.
This initial uniformity of HDP oxide film adversely affects the planarization [8]. In the case where the deposition of the film is "edge fast," that is to say, film growth takes place more quickly at the wafer's edge than at the center when the film is exposed to CMP, there is overpolish toward the edge of the wafer leading to increased localized dishing and erosion. To solve the problem, a novel single-wafer wet etching process is proposed for prior to the oxide CMP to diminish the film thickness variation. Its purpose is to correct the initial film nonuniformity, thereby enabling the subsequent CMP process.
Concept
Wet etching chemicals are supplied from a nozzle locally to a concentrated area of the wafer where the initial oxide is thicker than the other area. Preferably, oxide etching is done in the thicker oxide region of the wafer to enhance the global planarity. This planarization is achieved by using single-wafer wet etching equipment. Oxide in the central region is not exposed to the etching chemicals and, therefore, stays intact, because the wafer is rotating during the processing and the chemicals flow away toward the edge of the wafer due to the centrifugal force exerted on the chemicals. It is possible to avoid unnecessary thinning of oxide, located in the most peripheral region of the wafer (outside the thicker oxide region) by supplying high-temperature chemicals. The high-temperature chemicals are cooled down as they flow down toward the edge of the wafer.
 Figure 1. Example of decreasing etch rate on the wafer. |
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 Figure 2a. |
Since the etch rate is sensitive to temperature, much lower etch rates can be obtained at the most peripheral region where oxide is desirably not etched (Fig. 1). Cool-down of the chemicals is accelerated by nitrogen gas blowing on the backside of the wafer and by lowering the flow rate of the etching chemical to create a temperature difference between the region with thicker oxide and the central region of the wafer. Both changes lower the etch rate in the most peripheral region. Local chemical etching made in the thicker oxide region through these mechanisms leads to the enhanced global uniformity of HDP SiO2.
 Figure 2b. Result of global planarization on a) a blanket wafer (profile data); and b) on a patterned wafer. |
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Procedure
A 2.5% diluted HF was used as the etching chemical at 50°C with a flow rate <1 liter/min. Figure 2a shows HDP SiO2 thickness distributions across blanket and patterned wafers. After pre-planarization, the difference between maximum and minimum in the film thickness on the whole wafer was diminished from 37nm to 17nm, and the film thickness uniformity was improved from 11.8 to 5.4%, 3σ. Figure 2b shows the profile of film thickness before and after the chemical etching for STI patterned wafers, demonstrating that the thickness correction works effectively with patterned wafers.
The Si3N4 thickness distributions after CMP shown in Fig. 3 are of actual STI wafers with and without the film thickness correction. In this case, where no correction is made, the Si3N4 thickness is thinner in the central region and thicker in the peripheral region, reflecting the initial film thickness distribution. It is possible to correct this nonuniformity by applying the wet etch.
 Figure 3. Distribution of thickness on an STI pattern after CMP (Si3N2 on the active area). |
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Figure 4 shows the thickness distribution of oxide in STI trenches after CMP with and without the correction process. Remarkable differences have been observed between these two experiments. While the trenches processed without the correction step have a uniformity similar to that of the initial value, the thickness variation has been dramatically reduced after wet processing. The conventional dishing and erosion in the central region has been well suppressed by the correction step. The table summarizes these results — uniformity after CMP has been greatly improved without any detrimental effects.
 Figure 4. The distribution of thickness on an STI pattern after CMP (SiO2 on trench). |
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Simulation
It is possible to estimate the thickness distribution correction associated with this chemical etch process by investigating the etch rate and the etching profile of the wafer substrates in various dispense nozzle positions. The data can be used to optimize process conditions without using actual wafers, even if the profile of the film thickness changes before etching.
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The etch rate in each nozzle position and the etching profile in the unit time are investigated and the data are integrated with arbitrary processing time (Fig. 5a). The etch rate in each nozzle position on a wafer is also calculated (Fig. 5b). The thickness distribution after the correction is simulated by subtracting the profile of the etching amount obtained by the calculation from the thickness profile before the etching (Fig. 5c).
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The comparison of experimental results and calculated results in thickness distribution after correction is shown in Fig. 6. The experimental and calculated profiles were in agreement. Thus, the etching parameters can be easily optimized by using this simulation — when the film thickness profile is changed — by changing the conditions of the film deposition. This means the simulation method can be applied to a film correction with various thickness distributions.
 Figure 6. Comparison of the experimental results with calculated results in thickness distribution after correction. |
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Since the wet pre-planarization process both thins the surface film and corrects for nonuniformity, the burden on the CMP process step is lightened considerably. The pre-planarization step greatly diminishes the requirements of CMP process development, which is complicated and time consuming. It can also be argued that fewer CMP tools are needed to perform the steps in the process flow due to the decreased CMP times necessary per wafer.
Conclusion
The newly developed single-wafer wet chemical pre-planarization process can improve the overall surface planarity, as well as suppress dishing and erosion of oxide and the thinning of Si3N4 during CMP. It will also reduce the cost of consumables and increase equipment uptime for STI CMP because the frequent pad, carrier, and other parts change and adjustment normally required to keep STI planarity will not be needed. This correction process is expected to become more effective as the wafer size becomes larger where the initial film thickness tends to have larger across-the-wafer distributions. This process is also expected to be extendible to other ones that prefer uniform initial film thickness.
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Hayato Iwamoto received his BS and MS degrees in industrial chemistry from Meiji U. and is a senior manager in the Semiconductor Technology Development Group at Micro Systems Network Co., SONY Corp., Semiconductor Network Co., Atsugi, Kanagawa 243-0014, Japan; e-mail: [email protected].
Hajime Ugajin received his BS in electronics from Kogakuin U. and is an engineer in the Semiconductor Technology Development Group at Micro Systems Network Co., SONY Corp.
Kei Kinoshita received his BS in electronics from Hosei U. and is a manager in the Process Development and Applications Group at SEZ AG, Villach, Austria.