Topography reduction for copper damascene interconnects
08/01/2003
By Brian Stickney, Bang Nguyen, Bulent Basol, Cyprian Uzoh, Homayoun Talieh, NuTool Inc., Milpitas, California
Overview
Surface topography variations (currently >4000Å) within-die, die-to-die, and across the wafer, are major obstacles for the copper interconnect process today. Improving the planarity at the copper deposition step and reducing the amount of dishing/erosion at the CMP step can achieve topography reduction. Current process techniques have reached their limits, however, and new ones are required. A review of planarization methods is presented along with new techniques that can reach topography levels of <500Å with dishing <300Å.
Integrated circuits with copper damascene interconnects will have as few as five copper layers and possibly up to 20. The average number of interconnect layers for 90nm logic ICs is 9–11. As levels of interconnects are added to the IC, surface topography becomes more of a critical parameter that needs to be controlled both globally and locally, within-die, because topography variations translate into variations in post-CMP metal thickness, which in turn results in line resistance differences both within-die and die-to-die.
Furthermore, design rules for interconnect layouts — used to control the intra-die and die-to-die resistance — are constrained due to topography variation. Yield/performance is reduced if the topography is not tightly controlled. Topography variation is a function of the previous layer, dishing/erosion and device structures, and the copper deposition process. For example, CMP for the W plug process at the contact step generates high dishing and erosion values, which affects the dielectric used at the M1 step.
The most important source for within-die and die-to-die topography, however, is the copper deposition step. Step heights on the order of the feature depth, or more, can be found on a copper-coated wafer surface; most of this difference is between regions with narrow dense features and those with wide features [1]. An example of a wafer that received a typical electrochemical deposition (ECD) of copper is shown in Fig. 1. Leveler was used in the formulation of the electrolyte employed for this deposition to provide planarity for the nested features, but significant overburden thickness difference can be seen at the wide trench vs. the region with nested trenches; topography is 4000Å for this wafer.
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Topography
Traditionally, the process step that tries to eliminate the surface topography described above is the CMP step. However, CMP itself may introduce wafer surface topography. As each copper interconnect layer is fabricated by plating a copper layer and removing the copper overburden and the barrier by CMP, there is dishing of the metal lines and erosion of the dielectric. The dishing and erosion defects propagate from one layer to the next and as the number of layers increases, the topography on the wafer surface also increases [2].
To combat the topography added to the interconnect structure by the sources identified above, design rules for interconnects have been drastically tightened [3]. This limits the types and sizes of structures that can be placed at specific locations on specific layers. It also provides a CMP process window so that limited amounts of dishing occur on a single layer, thereby providing a tight distribution of line resistance within-die and die-to-die. By tightening the design rules, however, a price is paid in terms of reduced layout efficiency and increased number of interconnect layers, since using a minimum number of layers requires more relaxed design rules.
Table 1 illustrates the means through which planarity has been achieved in past and current technology nodes, as well as a projection as to how Cu deposition, planarity, and removal may be performed in the future.
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Planarization at the CMP step
Traditionally, the CMP process step planarizes and removes the copper overburden at the same time; it then removes the barrier metal. Therefore, during CMP, two operations are performed simultaneously. CMP, however, can only address topography reduction on a global scale — it cannot address the problems associated with intra-die and die-to-die variations.
Over the past few years, several developments have been made to achieve better planarization at the CMP step. Chemistries have been modified (improved selectivity to topography differences and materials), and softer pad materials have been implemented to reduce the amount of dishing and erosion.
Process tools have also continued to evolve, moving to processes with lower down force as an example, to address planarization capabilities as well as the change in materials to low-k and ultra-low-k (ULK) dielectrics.
The optimum result for both process performance and manufacturing are obtained with a hard pad, down force between 2–3psi, and selective chemistries. Soft pad material and lower down forces can be used to improve planarization and address the low-mechanical-strength dielectric materials, but there is a steep price to pay on the manufacturing end for throughput and COO.
Design changes have also been made to include the addition of dummy CMP structures on the wafer surface. These structures help even out the CMP process and provide a level of local planarization. Development of complex chemistries, new systems, layout changes, and design rule restrictions was in response to the fact that CMP is highly sensitive to pattern density and local topography [1, 4, 5]. As it exists today, CMP has reached its limit, and changes in the copper deposition process are required to extend the life of CMP as well as to find alternatives to the technology.
Current CMP technology performs best if the within-die and die-to-die topography is limited and there is little pattern density difference; that is, the wafer is planar before the Cu removal process is performed. If the wafer is planar, <300Å total topography, CMP sensitivity to topography and pattern density will be eliminated and the process window widened, thereby reducing and possibly eliminating dishing and erosion.
Planarization in the plating step
The copper process has two filling mechanisms: super fill for the narrow features (<0.8μm wide), and conformal fill for the wide features (>1.5μm wide). A single mask layer can have features that range from 0.1µm to >100µm. Originally, plating chemistries used two components, an accelerator and a suppressor. Use of the 2-component chemistries led to super filling of the narrow features that could not be easily stopped, and resulted in a bump or positive erosion over the nested narrow features [6]. Meanwhile, the large features filled conformally and would have a trough, or dishing.
For example, a layer with a 0.5μm-deep step in the oxide could have an average copper film thickness of 1.0μm in the field. Over the narrow nested features, the copper film thickness will be 1.4μm, or a positive erosion of 0.4μm. Meanwhile, in the wide features, the copper film thickness will be 0.6μm, or dishing of 0.4μm. A film with this profile will have topography of 0.8μm from the top of the positive erosion area to the bottom of the dishing area. The resulting CMP process in this case would have erosion of the narrow dense features and severe dishing of the wide features, to the point that little copper could be left in the lines.
To combat the super filling bump, or positive erosion, a third component — a leveler — has been added to the bath. The leveler reduces the amount of positive dishing so that a bump does not develop over the narrow dense features to the point that a locally planar film can be deposited. The amount of local planarity is defined by the feature size. Unfortunately, the leveler has a limited operating range, so planarization is only achieved for features with widths ≤2.5μm. For the above example, the topography could be reduced to 0.4μm by eliminating the positive erosion.
Limited planarization can be achieved in the plating step using a leveler, but this is not sufficient to relieve the design rule restrictions required to have a good CMP process. The ultimate solution is a copper-plated wafer that is fully planar before the CMP process.
To a lesser extent, AC wave forms, both pulse and pulse-reverse, have been implemented. The AC waveform provides less of an impact on planarization than addition of the leveler.
Planarization as an independent step
The copper removal step requires a fully planarized surface, total topography <300Å, to take full advantage of current CMP technology and offer alternative solutions to CMP. Meanwhile, the copper deposition process can only reach minimum planarity levels of ≥4000Å. What is needed is a way to bridge this gap.
One method to provide planarity without negatively impacting the removal process is to use a sacrificial copper layer that provides planar deposition. The sacrificial layer would be deposited onto an ECD copper-plated wafer with the result being an additional copper overburden but a final planarity <300Å. This planarization process would be insensitive to the existing topography and pattern density of the pre-processed wafer. One such technology for performing this planarization process is electrochemical mechanical deposition (ECMD) [7].
An example of the planarization capability of an ECMD film deposited on top of an ECD film is shown in Fig. 2. Here the planarity is ~200Å. These two structures were chosen because they represent the narrowest, ~0.14µm, and widest, ~100µm, features on this wafer. ECMD, when used for a sacrificial layer, has the ability to planarize incoming topography to <300Å for feature widths from 0.1µm to >1000µm. The level of planarization provided by the ECMD film translates into a wider CMP process window.
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Future trends
The future for copper interconnect holds two major challenges: integration of low-k and ULK dielectrics with low material strengths relative to silicon dioxide, and the X-initiative [8]. Migration to the new dielectric materials is already driving CMP processes to change with a focus on lower down-force pressures. Additionally, new copper removal techniques such as electrochemical mechanical polish (eCMP), and CMP-free or CMP-less process flows [9, 10] are in development. These techniques lower or eliminate the stress on the dielectric during the metal removal process.
An example of the enabling capability provided by planar copper films is shown in Fig. 3; here the wafer has received copper ECMD deposition to a field thickness of 1.0µm. The copper was then removed/thinned to 0.1µm using an electrochemical technique that does not have planarization capability. The planarity from the deposition is maintained during the removal process.
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Transition from CMP to electropolish or other noncontact methods of copper removal will be required as the dielectric material becomes softer. Planarization of the copper before the removal process will become essential for technologies to replace CMP, as the new removal techniques do not have planarizing capability (Table 2).
The X-initiative, while drastically reducing die size, adds new complexity to the interconnect process [8]. Metal lines will no longer run perpendicular to each other but at a different range of angles. Control of dishing and erosion with current CMP technology will become more difficult and the design rule restrictions tighter to realize the benefits. A planar copper film will eliminate many of the complexities and obstacles to full implementation of the X-initiative by removing the pattern dependence from the metal-removal process.
Conclusion
Planar copper films with <300Å topography will be required to overcome the obstacles facing integration of copper damascene technology. To achieve such requirements, the planarization process needs to migrate from the CMP process to an independent process step. The benefits of reduced topography include consistent intra-die and die-to-die sheet resistance, and a pathway to copper-removal techniques without the need for planarization.
Many benefits can be gained in having a planar copper film before the removal process. These include removing the pattern dependence from the metal-removal process; a wider CMP process window; an opportunity for eCMP removal processes; an opportunity for electropolish to replace CMP; an opportunity for wet etching to replace copper CMP; and full realization of the X-initiative.
Acknowledgments
NuTool is a registered trademark of NuTool Inc.; LuminCu, RL-CMP, and ECMD are trademarks of NuTool Inc.
References
- S. Hymens et al., "Evolution of Topography During 1st Step CMP of Cu-Plated Damascene Structures," Electrochemical Society CMP Symposium, Oct. 1999.
- T. Park et al., "Multi-Level Pattern Effects in Copper CMP," Electrochemical Society CMP Symposium, Oct. 1999.
- K.C. Yu et al., "Integration Challenges of 0.1µm CMOS Cu/Low-k Interconnects," IITC 2002.
- G. Banerjee, J. So, B. Mikkola, "Simultaneous Optimization of Electroplating and CMP for Copper Process," Solid State Technology, November 2001.
- T.I. Bao et al., "90nm Generation Cu/CVD Low-k (k<2.5) Interconnect Technology," IEDM 2002.
- S. Lakshimnarayanan, P. Wright, J. Pallinti, "Design Rule Methodology to Improve the Manufacturability of the Copper CMP Process," IITC 2002.
- B. Basol et al., "ECMD Technique for Semiconductor Interconnect Applications," Microelectronic Engineering, Vol. 64, p. 43, 2002.
- www.xinitiative.org.
- W.S. Shue et al., "CMP-Free and CMP-Less Approaches for Multilevel Cu/Low-k BEOL Integration," IEDM 2001.
- T. Nogami et al., "Newly Developed Electro-Chemical Polishing Process of Copper as Replacement of CMP Suitable for Damascene Copper Inlaid in Fragile Low-k Dielectrics," IEDM 2001.
For more information, contact Brian Stickney, NuTool Inc., 1655 McCandless Drive, Milpitas, CA 95035; ph 408/586-9500, ext 229, fax 408/586-9508, e-mail [email protected].