Junction scaling using lasers for thermal annealing
07/01/2003
Overview
The desire for ever-higher drive currents from MOS transistors has forced aggressive scaling of physical gate lengths over the past three decades, with no end in sight. Continued scaling alone cannot achieve significant performance improvement; however, source and drain resistances must also scale proportionately, since these are now significant compared to the channel resistance. Two laser-annealing techniques that provide a scalable path to achieve the ultrashallow junctions required for the 90nm through 20nm nodes are described.
As semiconductor manufacturing continues to follow Moore's Law, junction annealing has been forced to evolve to ever-shorter times and higher temperatures to limit transient enhanced diffusion and improve dopant activation levels. The latest generation of rapid thermal annealing (RTA) tools — in the regime of spike annealing — achieve sub-100-msec effective exposures near peak temperatures of 1100°C. It appears that scaling current lamp-based technologies beyond this regime will be difficult, forcing consideration of new technologies.
Two revolutionary technologies, combining projection optics and either pulsed or CW lasers, have been developed to address end-of-roadmoap junction annealing. Laser thermal processing (LTP), which achieves dopant activation in the liquid phase during nanosecond irradiation, is designed to break through all process barriers associated with advanced junction and contact formation from 90nm to the end of the roadmap. Surface emissivity variations associated with device structures, however, prevent direct exposure. Instead, these variations are managed in LTP using additional deposited films on the wafer surface.
Laser spike annealing (LSA), in contrast, activates dopants in the µsec-msec time frame staying in the solid phase. By appropriate tool design, this activation can be achieved uniformly without use of any additional process layers.
Three critical junction parameters must be simultaneously optimized for transistor performance: 1) junction depth, 2) sheet resistance, and 3) lateral abruptness [1]. Current junction annealing technologies (RTA) cannot achieve the desired junction characteristics for several reasons, including fundamental limits arising from dopant diffusion and solid solubility limits on activation [2]. For the near-term nodes, several process technologies are being pursued, including millisecond flashlamp spike annealing, laser spike annealing (LSA), and solid phase epitaxy (SPE) [3]. Given the defects and leakage associated with SPE alone, flashlamp and LSA technologies appear to be the more likely choices. In the longer term, liquid-phase LTP and selective epitaxy are being pursued to address junctions through the 20nm node. Thus, LSA is a near-term solution and LTP is for end-of-roadmap junction annealing.
Junction annealing
Junction annealing has evolved from simple batch furnace annealing to the current generation of lamp-based RTA systems. It is achieved by raising the entire wafer to temperatures of 1000–1100°C for ~1sec. Even at these temperatures and time scales, significant dopant diffusion can occur, and complete activation is nearly impossible. Improvements can come only by raising the temperature even higher while simultaneously decreasing the anneal time.
Previous research has demonstrated dopant activation from the nsec to msec time scales [4]. At temperatures just below the silicon melting point, only a few µsecs are required to achieve full activation; diffusion at such short times is almost negligible. LSA has been developed to provide junction annealing on these time scales. In this technique, a CW laser beam is scanned across a wafer to locally heat and anneal exposed areas as it passes. The peak annealing temperature is set by the laser power density and the anneal time by the scanning velocity. Annealing times of 10–200 µsec at temperatures up to 1350°C can be achieved (Fig. 1)
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In the LSA process, the wafer, mounted on an x-y linear stage, is scanned under a stationary shaped laser beam. Constant peak temperature is maintained by feeding back the pyrometer signal to the laser power attenuator. The simulated temperature profile for a 200-µsec anneal in silicon is shown in Fig. 2. For this simulation, the wafer scan speed is 500mm/sec under a 100µm-wide beam. Heating is limited to the near surface of the wafer with the backside remaining at essentially ambient temperature. With little of the wafer heated, the surface temperature drops rapidly, reaching <300°C within 4 msec (2mm behind the beam).
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Simple solid-phase heating cannot activate dopants on time scales <ηsecs. To achieve activation on shorter time scales, it is necessary to go into the liquid phase with activation during epitaxial growth. This nsec anneal technology is commonly referred to as LTP. A short pulse (10–100 nsec) laser is typically used to melt the surface. With liquid phase impurity diffusivities many orders of magnitude higher than in the solid phase, dopants diffuse throughout the melt, redistributing themselves uniformly. During the subsequent epitaxy, the dopant atoms are incorporated onto crystal sites, forming a near ideal junction with maximum concentrations limited only by crystal stability. An order of magnitude higher activation with atomically abrupt junctions has been demonstrated. A schematic of LTP hardware is shown in Fig. 3. The laser beam is homogenized and shaped to match the die size on the wafer (up to 30x22mm). Exposure of the wafer is then conducted in a step-and-repeat fashion, aligned to the device dies using a machine vision system. Only a single laser pulse is required to expose each die, with the wafer stepped between die, using an x-y stage.
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Figure 4 compares SIMS profiles from junctions formed by conventional RTA, solid-phase LSA, and liquid-phase LTP. The corresponding sheet resistances and junction depths for these are 350Ω/sq and 50nm for RTP; 250Ω/sq and 19nm for LSA; and 200Ω/sq and 13nm for LTP. Compared to conventional RTA, LSA and LTP simultaneously reduce the junction resistance and the junction depth. LTP junctions can achieve atomic abrupt doping profiles; the 1.5nm/dec measured abruptness is probably SIMS-resolution-limited. LSA junctions are only slightly less abrupt (1.9nm/dec), retaining the as-implanted profile. RTA, in contrast, is subject to significant transient enhanced diffusion, resulting in a 6nm/dec doping roll off.
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Pattern effects
The results described above clearly demonstrate the value of shorter time anneals, either in the solid or liquid phase. However, annealing at short time scales exacerbates pattern density and related effects on the wafer. On a bare device wafer, light absorption will be affected by the nature and density of the device structures. For example, oxide acts as an antireflective (A/R) coating and will always absorb more light and hence reach higher temperatures. As a result, large isolation areas and large active areas require different fluences for optimal activation. In conventional RTA, these geometry effects are minimized by 1) heating from the backside of the wafer (no patterns), and 2) thermal averaging across the wafer's front-side over the anneal time. For a 1-sec RTA anneal, thermal diffusion equilibriates temperatures over mm scales.
However, for nsec-msec annealing, thermal diffusion lengths are ~1–100ηm and only the illuminated side of the wafer heats, with the other side remaining close to room temperature. Consequently, it is necessary to irradiate the patterned side of the wafer to achieve activation. Similarly, thermal diffusion is no longer as effective for averaging out variations in surface temperatures. Pattern-dependent absorption must be explicitly controlled in order to scale annealing to <1 msec.
Solutions to the pattern effects, exploiting characteristics of the laser sources, have been demonstrated for both LSA and LTP. For LSA, the solution is based on hardware design, while thin-film engineering is used for LTP. During LSA, the thermal averaging distance is approximately 100ηm, large enough to directly image the emissivity variations using contrast maps for sample test die (Fig. 5). For these measurements, an 80ηm-dia. laser spot (corresponding to the thermal averaging distance) was scanned across the die while monitoring the reflected power. These data indicate that the high-contrast mode shows a variation of nearly 8.5% in the reflected (and hence absorbed) power. With simple modifications to the anneal process, this variation was reduced by almost an order of magnitude, a variation of only 1.5% shown for the low-contrast mode. Pattern effects can therefore be reduced to acceptable levels in LSA by simple hardware modifications.
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For LTP, the time scales are tens of nsecs and the pattern-dependent effects are much more pronounced. Lateral averaging by thermal diffusion is limited to only a few microns — adequate to average over single devices, but not between devices. Additional complications arise with the melt process, including morphological changes driven by the liquid surface tension. To address all of the issues, a series of thin films are deposited on the wafer surface prior to laser annealing. These films include an oxide or nitride barrier to prevent junction contamination, a high-melt temperature metal to act as a confining mold, and a silicon layer to act as an A/R coating at the specific laser wavelength. The A/R coating formed between the silicon cap and the metal layer eliminates the emissivity variations and provides nearly uniform absorption on all device structures. Further, with proper optimization of the three films, the silicon film can also act as a phase switch, significantly expanding the process margins.
Figure 6 shows an XTEM of a dense circuit area with 8nm junctions formed by LTP. Without the thin-film stack, absorption variations previously prevented activation of junctions in such dense areas. Today, by appropriate stack engineering, uniform activation can be achieved in all areas (Fig. 6).
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Conclusion
LSA and LTP have been demonstrated as viable solutions for junction formation both in the near term and to the end of the roadmap. Both are "near-zero" thermal budget processes, heating and cooling the surface temperature within µsec (LTP) or msec (LSA). In these time scales, processes that can degrade device performance — such as boron penetration through oxide or transient dopant diffusion — are kinetically suppressed and not observed. Average substrate temperature is never >50°C. Existing alternate thermal annealing technologies are limited to annealing in the several to several hundred-millisecond regime. On such time scales, even though the wafer can be rapidly brought to the anneal temperature, cooling remains difficult, as the entire substrate reaches 900–1050°C. Ramp-down rates are limited to 60–150°K/sec, resulting in total thermal budgets comparable to present-day RTA. LSA cooling rates are nearly three orders of magnitude faster (2x105 K/sec), with LTP an additional three orders of magnitude.
The unique characteristics of LSA and LTP also enable their use as a local area processing technology. With the short, effective annealing time, a simple mask layer could be used to modify the annealing conditions on various elements of a chip — limited only by the thermal diffusion length.
Pattern density related nonuniform heating will be a significant issue for any technology that reduces the anneal time. One potential solution is modification of layout rules to achieve uniform density of all film stacks within a thermal diffusion length (defined by the anneal time). Although possible, this is very difficult for many products such as SoC. For both LSA and LTP, such modifications are either unnecessary or at least dramatically reduced. For LSA, pattern dependencies are minimized by tool hardware modifications, while for LTP, the issue is resolved using additional thin-film coatings.
Although developed for source/drain annealing, it is clear that many more applications for these two technologies exist. LTP has been shown to be beneficial during gate doping for reduction of poly depletion, and in deep source/drain formation for reduction of contact resistance. In the future, LSA and LTP can be used for many BEOL applications such as copper and low-k dielectric annealing. These processes have traditionally been performed at low temperatures due to thermal budget concerns; laser annealing can enable the use of higher temperatures for the purpose while still limiting the net thermal budget.
As device manufacturers integrate additional functionality into chips, an annealing technology that imposes a low thermal budget, is pattern-density independent, spans a wide range of time-temperature space, and provides improved junction performance over RTA will be critical. LSA and LTP meet all of these requirements and are ideally suited to replace RTP for advanced junction formation.
Somit Talwar, David Markle, Ultratech Stepper Inc., San Jose, California
Michael Thompson, Cornell University, Ithaca, New York
References
1. Y. Taur, C.H. Wann, D.J. Frank, IEDM Tech Digest, p. 789, 1998.
2. S. Sishiguchi, A. Mineji, T.Y. Matsuda, H. Kitajima, Electochem. Soc. Symp. Proc. 99-10, p. 109, 1999.
3. S.B. Felch et al., Ion Implant Technology Conference Proc., IEEE, p. 351, 2000.
4. S. Talwar, S.B. Felch, D.F. Downey, Y. Wang, Ion Implant Technology Conference Proc., IEEE, p. 215, 2000.
For more information, contact Somit Talwar, VP of laser technology at Ultratech Stepper, 3050 Zanker Rd., San Jose, 95134; ph 408/321-8835, e-mail [email protected].