Using an HDP reactor to make barrier stack etches for MEMS devices
07/01/2003
Overview
Corrosion resistance, electromigration resistance, and compatibility with standard IC fabs make platinum attractive as an interconnect in MEMS applications. Platinum and lead zirconate titanate etch rates greater than 1000Å/min are possible at moderate (80°C) wafer temperatures using photoresist masks in a high-density plasma etch system. Etch profiles with no post-etch residue for metal-ferroelectric-metal stacks like those used for a MEMS-based atomic force microscopy application, for example, which employs a bottom platinum layer = 1500Å, 2800Å of lead zirconate titanate, and a platinum top electrode = 1500Å, can be achieved. Production data from a process for etching a platinum/titanium-tungsten stack for a micromachined mirror device are also presented.
Similar to those processes used by the large integrated device makers for high-volume CMOS products, the basic sequence of thin film deposition, photolithography, and etch is repeated many times to make a finished MEMS device. However, the many novel structures and materials cause MEMS fabrication to diverge in several important ways from the family of standard silicon-processing modules.
Fabrication challenges
Materials is one area of divergence between MEMS and CMOS fabrication. Lead zirconate titanate (PZT), for example, is useful for many different MEMS applications, most prominently those requiring physical motion, like moving mirrors in optical switch fabrics, and those for which the ability to adjust device capacitance is important, such as acoustic filters for RF communication applications. In addition, the oxidizing environment found during the deposition and annealing of PZT films means that some electrode material capable of resisting oxidation (platinum) or capable of forming an electrically conductive oxide (iridium) must be used in conjunction with PZT, hence the name, metal-ferroelectric-metal (MFM) stack. This is very different from the capacitor structures and metallization schemes found in CMOS processing, where the dielectric materials are typically silicon dioxide or silicon oxynitride, and the electrode materials silicon, polysilicon, or aluminum and aluminum alloys.
Platinum has many advantages over conventional interconnect materials in MEMS applications. Various biological MEMS devices need electrodes that are corrosion resistant to survive the harsh fluids to which they will be exposed. Micromachined mirrors, another good example, have very stringent stress requirements and often operate at high voltage or current. The good electromigration resistance of platinum meets these needs, allowing the electrodes to be thin without increasing linewidth requirements. Additionally, the stress requirements or novel packaging techniques of MEMS often necessitate unpassivated metal or a noble metal bond pad. Platinum provides good reliability for both, with the added benefit of being more compatible with silicon fabs than gold.
Patterning these structures is inherently challenging. Due to the nonvolatility of the etch products produced during MFM stack etch, or platinum etch, it is difficult to successfully integrate the etches into microelectronic devices [1, 2]. Some candidates for subtractively patterning (etching) these difficult materials are wet etch, chemical-plasma etch, reactive ion etch, and ion milling. Each, however, has its problems.
 Figure 1. Veil formed after dry etch of platinum. |
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Wet etching generally suffers from feature size limitations and scalability issues, while chemical-plasma etching offers only limited etch rates, particularly for noble metal and heavy metal thin film applications. Ion milling, or ion beam etching, is a versatile tool that has been used in laboratory applications for patterning almost any known material. An ion beam can be made to be sufficiently energetic to remove atoms from surfaces on which the beam impinges under temperature and pressure conditions where the vapor pressure of the material(s) to be removed is negligibly small.
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For this reason, ion milling lends itself perfectly to laboratory demonstrations of MFM capacitor formation, where the problem of patterning the noble metal electrodes, noble metal interconnects, and the heavy metals in the ferroelectric films, does not warrant extensive exploration of other patterning techniques as it does at the feasibility stage of device fabrication.
Researchers have noted several drawbacks to ion milling for actual production, however. When ion milling is used to pattern platinum, the removal rate of platinum is low (~400Å/min); the overall tool throughput, as a result of the combination of low etch rates and the need for long overetches, is poor; and the tendency of the etched material to redeposit on the side of the etch mask, and remain, causes the formation of veils, or fences, after the etch mask has been removed. These veils can lead to yield-limiting electrical defects in finished devices. Figure 1 is an example of the kind of veil observed post-etch (and after photoresist mask removal) for a dry-etched platinum feature.
Also, in MEMS devices (particularly mirrors), film thicknesses, such as for the etch stop layer, must always be minimized. The selectivity, uniformity and overetch requirements of ion milling further preclude its use. These shortcomings have motivated the industry to develop alternative dry patterning processes for MFM stacks, including plasma etch.
Plasma etch is used in modern microelectromechanical fabrication processes to faithfully reproduce masking image features into the permanent layers of a device or circuit. The benefits of plasma etch include the ability to etch submicron structures, or very deep structures, without changing critical dimensions while maintaining good selectivity to the masking and underlying materials.
Experimental
One specific etch process module used for this work is a dual frequency, magnetically confined plasma etch reactor capable of producing high-density plasma conditions at low (1mtorr–100mtorr) discharge pressures. In this reactor, RF power at MHz frequencies produces the dissociated, reactive, and ionized components of the etching plasma. A second RF frequency, in the kHz range, acts to control the energy of ions impinging on the wafer surface.
 Figure 2. Response of platinum veil height (Å) to MHz power and Cl2 (sccm) flow. |
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A dual frequency plasma reactor, when the separation between the two RF frequencies is large, can be made to act independently on plasma density and ion energy. For etching materials like platinum and PZT in a plasma reactor, the physical component (ion energy) of the etching will be one of the chief means by which the thin films are removed from the wafer surface. 100kHz, 400kHz, and 450kHz are examples of standard frequencies used by plasma tool manufacturers for this task, and 13.56MHz is the RF frequency commonly used to generate and sustain reactive etching plasmas.
RF power in the dual frequency reactor is capacitively coupled to the plasma, making power transfer, and hence process stability, impervious to deposits formed on the inner surfaces of the reactor even if those deposits are electrically conductive, as will be the case when etching noble metal electrode films like those found in MFM stacks. The reactive plasma generated in the dual frequency reactor is augmented through the use of magnetic confinement. Permanent rare-earth magnets mounted on the reactor sidewall and on the top electrode are placed so that they reflect escaping free electrons back into the active plasma region, thereby increasing the electrons' useful life in the reactor, and extending their contributions toward sustaining the plasma overall. It is this magnetic confinement that creates the high-density plasma conditions within the reactor.
Optimizing plasma etch for MFM stacks
Table 1 summarizes some of the physical properties of the important chlorides formed when platinum and PZT are etched in chlorine-containing plasmas.
The volatility of the Pb, Pt, and Zr etch products is considerably less than those of other elements commonly etched in plasma reactors, like silicon and aluminum (and much less than that of TiCl4, which behaves "normally"). Low volatility of the etch products here suggests that etch rate issues and post-etch residues created from nonvolatile etch products landing on adjacent surfaces are likely to be encountered when plasma etch techniques are used to pattern these films. (Another issue that will arise is the question of MFM stack etch process manufacturability; the number of wafers that can be etched before the plasma reactor must be cleaned is directly related to the nature of the etch products formed during the plasma etch process.)
A key finding from historical efforts to optimize MFM stack etch in plasma reactors is that, in a reactive environment like an argon-chlorine-based plasma, the etch rates of platinum and PZT increase when their surfaces are bombarded by ions of increasing energy and that veil formation can be controlled by adjusting the reactive (halogen) component mole fraction either by increasing its flow or by increasing the dissociation of the etchant gas in the plasma (Cl2 ®Cl) [3].
MFM stack etch data
Etch rates and post-etch veil formation for platinum films masked with photoresist were characterized in the dual frequency capacitively coupled plasma reactor described previously. This characterization was performed using design of experiment (DOE) techniques, which are useful because they reveal process trends and process interactions for multivariable systems.
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The principle process variables, or experimental factors, in a plasma etch reactor are pressure, temperature, type of reactant used, reactant flows, reactant fraction (in multireactant chemistries), plasma density, and ion bombardment energy and flux at the wafer surface. The effect MHz power and Cl2 flow have on post-etch veil height (where a veil height of zero is the best possible result) for a photoresist-masked platinum film is presented in Fig. 2.
Optimized MFM stack etch
Plasma etch for stacks are often performed using two separate masking steps, a process that can be used to create a common bottom electrode for an array of MFM structures when desirable. Another important consideration is wafer temperature. By keeping the wafer temperature low (~80°C) during the MFM stack etch, photoresist masks are readily accommodated by the etch processes reported here.
Figure 3 is a SEM micrograph showing a completed MFM stack (Pt/PZT/Pt) etch performed in the dual frequency capacitively coupled plasma reactor. The micrograph shows the etch profile after photoresist mask(s) removal. The complete stack has been etched veil-free using photoresist masks.
 Figure 3. Etched MFM stack (Pt/PZT/Pt) with photoresist mask(s) removed. |
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 Figure 4. Etched Pt/TiW stack with mask removed. |
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Table 2 summarizes the MFM stack etch results obtained with an optimized plasma etch process in the dual frequency capacitively coupled plasma reactor for platinum and PZT films using photoresist masks.
Pt/TiW stack etch
The results obtained for etching platinum in MFM stacks can be directly applied to etching a platinum interconnect stack. In the application reported here, a 2000Å Pt layer is deposited on a 400Å TiW barrier/.adhesion layer and directly etched using a photoresist mask.
This metallization scheme has been chosen for a micromachined mirror device for several reasons: 1) the advantages noble metals have for packaging requirements; 2) a platinum interconnect can remain thin while satisfying the large current-carrying requirements of the device; and 3) processing platinum, unlike gold, is compatible with the silicon IC fab work required to fabricate active elements for the mirror position sensing. Because adhesion of Pt to thermal SiO2 is poor and a barrier layer is needed to prevent the Pt from reacting with the silicon substrate, a TiW layer is required. Another significant challenge to the etch process is that loss of the 1000Å SiO2 etch stop has to be minimized because a certain thickness is required to adequately passivate the active devices.
While the profile of the etched feature is not critical to this particular device, it must still be controlled to help prevent the formation of sidewall veils and corrosion. As a result, the etch process must accommodate the normal variation in photoresist profile. In addition, the etch process must not produce microtrenching into the oxide at the edge of the etched feature. Figure 4 is a SEM showing a cross section of the edge of an etched feature after photoresist removal. The feature is etched to completion with no sidewall residue or microtrenching.
To confirm that the etch process has a normal sensitivity to resist profile, platinum features etched with photoresist formed under various patterning conditions were measured for CDs and then checked for completion of strip and veil formation. While the photoresist process affects the CD as expected, all conditions strip cleanly and are free of polymer veils.
For this process, the critical parameters to monitor in production are both the platinum etch bias consistency, since the overlay and metal line resistance requirements demand <0.4ηm linewidth variation, and post-etch oxide etch stop thickness. Figures 5 and 6 show the process performance through the first 30 production runs.
 Figure 5. Production etch bias performance. |
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 Figure 6. Production selectivity performance. |
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 Figure 7. Optical endpoint trace for a Pt/TiW stack. |
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In addition to these critical in-line parameters, endpoint times are tracked and used for statistical process control to monitor etch rate. The endpoint monitor triggers on completion of the TiW film (Fig. 7). This process has shown excellent consistency of etch rate with a mean endpoint time of 67.54 sec and a standard deviation of 1.15 sec for production runs to date.
Conclusion
Using a dual frequency capacitively coupled HDP reactor, plasma etch processes for two platinum-based MFM and platinum/barrier interconnect structures used in MEMS device fabrication were characterized. Experimental models derived from DOE methodology demonstrate platinum and PZT etch rates >1000Å/min at moderate (80°C) wafer temperatures.
Post-etch veils or fences can be eliminated using process conditions optimized with the same DOE techniques. Good etch profiles with no post-etch residues have been produced for MFM stacks like those used for a MEMS-based AFM application, which consists of a bottom layer of platinum 1500Å thick, 2800Å of PZT, and a platinum top electrode of similar thickness to the bottom electrode [4].
Production data on a metal etch process for a platinum and titanium tungsten stack used as metal interconnect for a MEMS mirror have also been presented. This process shows consistent results in terms of CD control, residue control and etch stop loss with manufacturing scale throughput.
P. Werbaneth, J. Almerico, L. Jerde, S. Marks, Tegal Corp., Petaluma, California
Bruce Wachtmann, Analog Devices, Cambridge, Massachusetts
References
1. T.C. Taylor, H.A. Harper, "Chemically Assisted Etching of PZT-based Ferroelectric Dielectrics and Noble Metal Capacitor Electrodes," Proceedings of the 20th Annual Tegal Plasma Seminar, pp. 41–81, 1994.
2. H. Takasu, "The Innovation on Semiconductor Devices by Using the Ferroelectric Memory Technology," Proceedings of the 24th Annual Tegal Plasma Seminar, pp. 11–17, 1998.
3. Y. Ito et al., "High Temperature Etching of PZT/Pt/TiN Structure by High Density ECR Plasma," Proceedings of the 20th Annual Tegal Plasma Seminar, pp. 83–86, 1994.
4. H. Nam et al, "Fabrication and Characterization of Piezoelectric PZT Cantilever for High Speed Atomic Force Microscopy," Proceedings of the Twelfth International Symposium on Integrated Ferroelectrics, Part VI, R. Waser, D. Wouters, R. Whatmore, editors, pp. 185–197, Gordon and Breach Science Publishers, 2001.
For more information, contact Paul Werbaneth at Tegal Corp., 2201 S. McDowell Blvd., Petaluma, CA 94954; ph 707/765-5608, fax 707/773-3015, e-mail [email protected]; or Bruce Wachtmann at 21 Osborn St., Cambridge, MA 02139; ph 617/761-7162, fax 617/761-7060, e-mail [email protected].