Moving from today's SOI to advanced substrate engineering
07/01/2003
Overview
As IC technology continues to grow, there will be an increasing need for engineered substrates tailored for specific applications. A viable route grows on wafer engineering that is already used for a high percentage of SOI wafers today. While R&D is continuing, there is promising work already done with the development of strained silicon-on-insulator, silicon-on-quartz, and germanium-on-insulator substrates.
The successful Smart Cut process, which was originally developed to manufacture Unibond silicon-on-insulator (SOI) wafers, is now emerging as a process with significantly more potential. Today, we can think of Smart Cut as a generic layer transfer technology that fills the gap between heteroepitaxy and single crystal thin film transfer to any type of substrate. This view substantially widens the field of engineered composite substrates combining different thin layer materials on a given substrate and addresses the requirements of most diverse applications.
SOI and 300mm
New emerging applications are rooted in the success of this process for high-volume production of SOI wafers with consistent quality [1–3]. It was just five years ago, with the opening of the first SOITEC facility, Bernin I, that SOI moved from the pilot line to mass production. Bernin I is now fully equipped, with a capacity of 800,000 (200mm equivalent) wafers starts/year. With the ramping of Bernin I, we have accumulated expertise with 100–200mm wafers and are able to respond to the needs of the evolving market [4–7]. Unibond SOI wafers in all diameters up to 200mm are today qualified in production by customers for applications ranging from thin films to thick films (Fig. 1).
null
Expertise gained in 200mm has readily scaled to 300mm. 300mm Unibond feasibility was initially demonstrated in 1997; the first samples were built in 2000. A 300mm pilot line has been operational since March 2002, and we are now in full ramp-up. Surface nanotopography improvements are proving particularly beneficial, and will prove invaluable as we move into the next generations of ultra-thin products and advanced engineered substrates.
Ultrathin SOI
The industry has an impending need for thinner SOI (Table 1). Ultra-thin SOI, where the top silicon layer is <500Å thick, provides users with enough process window to design at the 65nm node.
 |
null
The key challenges to fabricating ever thinner SOI are "nano" uniformity and accurate metrology to measure uniformity. In a fully depleted transistor architecture, the device performance is tightly linked to SOI silicon layer thickness. To guarantee parameter reproducibility over all devices, silicon film thickness has to be strictly controlled. This device-SOI interdependence leads to a 10Å thickness accuracy requirement. As a general trend, it looks like such high uniformity needs to be guaranteed for all spatial wavelengths of the measurement, down to the angstrom scale, which is currently the domain of roughness measurement. "Nano-uniformity" will certainly be the key challenge facing metrology.
From our development work, we know that Smart Cut technology can be extended to very thin films, both for silicon and oxide layers. We are already running 500Å silicon films over oxides down to 1000Å in production. Both 500Å over oxides below 1000Å and 200Å silicon on oxides down to 800Å are in advanced prototyping. Also, 100Å silicon over <200Å oxide Unibond feasibility has been recently demonstrated.
Our present production is designed for ±50Å uniformity in the top silicon layer for the UT1 process generation (see Table 1). This is 6s uniformity with each 200mm wafer measured at more than 1700 points and each 300mm wafer at 4000 points. In a typical 200mm example, we are able to control wafer-to-wafer mean thickness variation to ±15Å and on-wafer thickness variation to ~4.5Å. For some UT1 product lines, the top silicon layer thickness uniformity is reduced to ±30Å (6σ).
Surface roughness, which we have determined is very well controlled to ~2Å RMS (Fig. 2), is a key parameter in uniformity at these levels. Si/BOX interface roughness also exhibits low values, typically <2Å RMS.
We are also seeing a capability of ±50Å total uniformity (3mm edge exclusion) with our 300mm UT1 process, which is being ramped up. All characterization parameters for 300mm, including defect density, roughness, HF defect density, Secco defects, metallic contamination and electrical properties exhibit the same results as those obtained from high-volume production of 200mm wafers.
As we look forward, the UT2 generation exhibits standard deviations <5Å with a 3mm edge exclusion on 300mm wafers. Combined with a ±5Å control of wafer-to-wafer mean thickness, UT2 requirements translate to a ±20Å overall uniformity for 200Å silicon over 1500Å oxide SOI wafers. In recent work, improvements in splitting and surface finishing have resulted in surface roughnesses of 1Å and 3.5Å RMS for 1x1ηm and 10x10ηm AFM scans. However, there is a tradeoff between top layer silicon uniformity and the reduction of surface roughness. The process requirements to achieve a surface roughness as low as 1Å RMS degrade the overall top silicon layer uniformity. Our UT2 product generation optimizes layer thickness while keeping RMS surface roughness within the requirements of the 65nm node.
 Figure 2. AFM scans to measure surface roughness on UT1 SOI wafers; a) 1x1ηm scan yielding 1.5?? RMS and b) 10x10ηm scan yielding 2.7?? RMS. |
null
Our first development results on wafers for the XUT SOI generation, work done with 200mm 520Å silicon on 1450Å oxide wafers, demonstrates that <2Å thickness standard deviation is achievable. We have achieved the same performance with 300mm wafers, where on-wafer uniformity is compatible with ±10Å overall distribution, for all wafers on all sites (Fig. 3).
null
Strained silicon-on-insulator
Strained silicon is one of the latest substrate developments proposed for the manufacturing of very high performance devices. However, strained silicon on bulk wafers is still far from attaining the specifications of state-of-the-art silicon and SOI wafers. This is a crucial missing element in the move to high-volume strained silicon-on-insulator (sSOI). With basic SOI, we have ready availability of high quality, low-cost bulk silicon donor wafers from which we can transfer the top layer. But in the case of sSOI, the donor wafer is fabricated in several epitaxial steps. To successfully meet the industry's low cost-of-ownership (COO) requirements for sSOI, substantial effort has to be put into bringing down the cost and increasing the quality of the donor wafers.
The production of strained silicon substrates requires several silicon and silicon germanium (SiGe) epitaxial steps to obtain the strained silicon layer on the surface of a wafer. The strained silicon film is epitaxially grown on relaxed Si1-xGex. The degree of strain achieved is a function of the germanium percentage.
Research has shown that an enhancement of the electron and hole mobility of ~50% can be achieved as a function of the level of the built-in strain in the silicon lattice, which translates into improved MOSFET performance [8–12]. Strained silicon films grown on the SiGe epitaxial layers (relaxed layer plus buffer layer) on bulk silicon substrates with 20% SiGe epilayers are commercially available today, with dislocation densities between 104–106 cm-2 and strained silicon films ~20nm thick. But experience has shown that the COO is still too high.
There is a correlation between germanium content of the SiGe film and crystal quality of corresponding epitaxial layers. The challenge is that there is a critical thickness above which the strain in the silicon film relaxes, impairing film quality. As the Ge content increases above 20%, the thickness of the epitaxial strained silicon decreases.
Our research has shown that Smart Cut enables the development of ultra-thin strained SOI, which will be needed for fully depleted MOSFETs at the 65nm IC technology node. Further, we believe this can be done while reducing the overall cost of such high-end substrates. However, to bring this technology to volume manufacturing, Smart Cut and epitaxial development need to be part of the same effort. In order to ensure compatibility with high-volume production and reduced COO, we have recently expanded our development efforts to include the epitaxial processes.
By transferring a thin layer of the relaxed Si1-xGex from a starting epitaxial substrate to an oxidized handle wafer, an SOI-like structure is obtained that combines the advantages of higher mobility with those typical of SOI (Fig. 4). The synergy between ultra-thin SOI (<500Å Si on oxide) and ultra-thin strained silicon is one factor that makes the fast development of this new 300mm wafer generation possible.
Briefly describing the steps in making sSOI, the bilayer of strained Si and relaxed Si1-xGex is transferred, and in a second step the Si1-xGex is etched selectively to the strained Si (Fig. 5). The strained Si film thickness is 150Å ±15Å. In spite of the removal of the SiGe layer, the strain of the Si film is preserved by the bonding step (Fig. 6) [13].
Annealing experiments also show that the strain of the transferred strained Si film is clearly preserved up to 900°C. There is a small change in the strained Si signal and peak position in the 950–1000°C range. The effect on the strain of the transferred film during additional post-processing is under evaluation.
null
Silicon-on-quartz
The potential for Smart Cut technology goes far beyond just SOI and sSOI. For example, we are currently developing silicon-on-quartz (SOQ) — a single crystal silicon layer on a fused silica substrate. This work will be extendable to silicon-on-glass (SOG). SOQ marks the first time the industry can apply state-of-the-art expertise in silicon IC integration with substrates that are characterized by their transparency at visible wavelengths as well as by their electrical insulation. Depending on the characteristics, target applications include flat panel displays and CCD or CMOS imagers on one hand, and RF or HF devices on the other hand.
With respect to display applications, our ability to associate a single crystal silicon layer with a quartz wafer enables an increase in the integration or the resolution of the display. It also lowers power consumption, which takes it one step further than polysilicon technologies. Considering RF and HF applications, SOQ offers a low cost alternative to SOS, associating a perfect single-crystal silicon layer on a high purity fused silica substrate.
 Figure 5. TEM showing sSOI obtained by Smart Cut. TEMs of the initially transferred SiGe/strained Si on insulator (left) and after removal of the SiGe layer (right). |
null
SOQ technology is especially challenging because of the mismatch of thermal expansion coefficients between quartz and silicon. However, our results suggest that the main issues have been solved. Our first SOQ products consist of 200mm wafers, including a 200nm thick Si layer that withstands >1000°C high temperature processing (compared to 650°C for silicon on borosilicate glass).
 Figure 6. Raman scattering measurements indicate that the strain of the transferred layer is maintained after the SiGe removal. |
null
The SOQ SOG development roadmap includes high temperature SOG and ultra-thin Si (<100nm) on quartz (UT-SOQ) comprising a thinner Si layer for fully depleted MOSFET architecture and very high-performance IC integration. The roadmap also includes thick (>500nm) SOQ to assess applications based on the electro-absorption capabilities of Si.
Figure 7 maps a 200nm SOQ with a typical silicon layer uniformity of 75Å (3σ) and a 5x5ηm AFM scan surface roughness of 1.7Å RMS. Extensive characterization of the crystal quality has been carried out, including TEM observation, Raman spectroscopy, and x-ray diffraction. All three techniques confirm the high quality of the Si single crystal layer. Specifically, high-resolution TEM shows that the Si-oxide interface is sharp, that the transferred Si film is of very high crystal quality, and that there are no dislocations in the finished SOQ.
 Figure 7. Thickness map for a 200mm SOQ wafer (200nm of Si, 75Å 3σ, ±20Å total thickness variation). |
null
Germanium-on-insulator
Germanium-on-insulator (GeOI) on a silicon substrate is another very promising development of heterosubstrates. Ge offers a higher mobility than silicon. It is analogous to SOQ in the sense that the thermal coefficients of Ge and Si do not match. If combined with a GaAs epitaxial step, GeOI is of interest for manufacturing solar cells.
Also, GeOI is well suited for the formation of high-k gate oxides, which are deposited in an oxygen rich atmosphere. The advantage of germanium is that unlike silicon, it does not form a stable native oxide; therefore, no intermediate oxide forms under the high-k dielectric. Furthermore, electron and hole mobilities are much higher than in silicon.
An engineered wafer consisting of a thin layer of germanium and a silicon dioxide layer on a silicon substrate could well be the ultimate version of a mobility-enhanced, strained silicon device architecture approach.
Overall, the development of hetero-composite substrates, such as SOQ and GeOI can be used in applications for photonics, optoelectronics, high frequency, and high power devices. These trends show how substrate manufacturers can take more responsibility in the making of ICs, through the development of more complex, partially processed substrates tailored to specific applications. More visibility into the IC integration process will be needed to enable wafer manufacturers to develop suitable wafer solutions, in a similar manner to the evolution seen among the equipment manufacturers in the 1990s.
Carlos Mazuré, Ian Cayrefourcq, Bruno Ghyselen, Fabrice Letertre, Christophe Maleville, SOITEC SA, Bernin, France
Acknowledgments
Though most of the work covered in this review is the result of the R&D work of several teams, we single out the support received by the R&D and manufacturing divisions of SOITEC and the Laboratory for Film and Circuit Transfer of LETI-CEA in Grenoble. Special thanks go to André-Jacques Auberton-Hervé and Emmanuel Aréne of SOITEC, Bernard Aspar and Nelly Kernevez of LETI-CEA, and all SOITEC engineering teams. Smart Cut and Unibond are registered trademarks of SOITEC SA.
References
1. M. Bruel, US Patent 5,374,564 issued 12-20-1994 (US patent filed 9-15-1992, preceded by a French filing on 9-18-1991).
2. M. Bruel, Electron. Lett., 31 (14), p. 1201, 1995.
3. M. Bruel, Nuclear Instr. and Meth. in Phys. Res. B, 108, pp. 313–319, 1996.
4. A.J. Auberton-Hervé, C. Maleville, 2002 IEEE SOI Conference, p. 1.
5. C. Maleville, et al., 2001 IEEE SOI Conference, p.155.
6. A.J. Auberton-Hervé, et al., Electrochem. Soc. Proc., 99-3, p. 93, 1999.
7. C. Maleville, et al., 2002 IEEE SOI Conference, p. 194.
8. K. Rim, et al., Symp. VLSI Technology, p. 59, June 2001.
9. M.V. Fischetti, S.E. Laux, J. Appl. Phys. 80, pp. 2234–2252, 1996.
10. Z. Cheng, et al., IEEE Electron Device Letters, 22 (7), pp. 321–323, 2001.
11. J. Welser, et al., IEEE Electr. Dev. Lett. 15, 100, 1994.
12. Z. Cheng, et al., Symp. Proc. 686, A.1.5.1, 2002.
13. B. Ghyselen, et al., 2002 ICSI3 Conference.
For more information, contact Carlos Mazuré at SOITEC SA, Parc Technologique des Fontaines, 38926 Berin Cedex, France; ph 33/4-76-92-76-65, fax 33/4-76-92-76-60, e-mail [email protected].