Technology News
06/01/2003
Research chips away at the 45nm node
IMEC has achieved some promising process and electrical results in its search for alternative CMOS device architectures for the 45nm node and beyond.
Its Emerging Alternative Devices (EMERALD) program, which is open to industrial partners, is looking for manufacturable alternatives that remedy difficult-to-control short channel effects with physical gate length below 50nm and high gate-tunneling currents as oxide thicknesses fall below 2nm.
 Figure 1. Tilted view of a set of "fin" transistors after gate etch (Wfin = 50nm2, Lpoly = 42nm). |
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Using simulation, materials characterization, and device fabrication, IMEC, Leuven, Belgium, is studying high-k alternatives to SiO2, metal gate materials alternatives to polysilicon, multiple-gate device structures, and ways to increase channel mobility over unstrained inverted silicon. The EMERALD program is focusing on three specific device structures: fully-depleted (FD) silicon-on- insulator (SOI), multigate devices, and high-mobility Si-SiGe CMOS.
According to Serge Biesemans, manager of the device technology research department, the researchers have "demonstrated ultra-thin-film FD SOI CMOS circuits with a silicon thickness of 30nm using selective epitaxial growth (SEG) of silicon to form raised source-drains. High-performance 70nm and below gate-length FD-SOI CMOS transistors have been realized using a unique fabrication sequence, referred to as spacer-replacer. This allows halo-extension implants to be carried out after epitaxial growth."
Good drive currents at Vdd = 1.2V and for tαx = 1.6nm have been obtained where Ion = 680ηA/ηm and 310ηA/ηm and Ioff = 10nA/ηm for NMOS and PMOS, respectively.
Recent work with multiple-gate devices has been focused on the development of all required process steps. Here, double and triple gate device architectures are based on "quasi-planar" FinFET fabrication with active areas defined by e-beam lithography (Fig. 1).
Nadine Collaert, an IMEC process engineer, says, "For double-gate devices, an isolating layer is present on top of the active area. Different splits in sacrificial oxidation have been processed, using a 2nm thick nitrided oxide and a 100nm poly-gate stack. A second e-beam lithography step was used to define gate dimensions down to 50nm. Encouraging CMOS electrical results have been achieved."
With work on high channel mobility Si-SiGe CMOS devices, focusing on pFET devices with strained SiGe channels, pFET mobilities as much as 50% higher than universal mobility have been measured in long channel devices. This has led to work on strained-Si CMOS.
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Process engineer Peter Verheven says, "We are looking at several process routes to make transistors with a strained silicon top layer of sufficient quality. The possibilities of growing selective and nonselective epitaxial layers for the underlying SiGe buffer are being explored, as well as the effect of SiGe virtual substrates on standard CMOS processing steps."
Verheven added that good results have been obtained from building a shallow trench isolation (STI) on a SiGe strain relaxed buffer (Fig. 2) and that device experiments using the thin nonselective buffer approach are now in process.
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At IMEC, in exploring the concept of metal gates for use in high-k gate stacks, conventionally etched HfO2-based polysilicon and TaN-gated NMOS devices, featuring gate lengths down to 65nm, have been manufactured.
Mark Heyns, director of IMEC's department of ultra-clean processing, high-k dielectrics, and epi, says, "Functional HfO2-based transistors, have been demonstrated. Employing metal-gated high-k stacks not only eliminated the gate depletion observed with polysilicon, but also improved EOT and CET scaling performance and drive current due to less interaction between high-k materials and the gate electrode." See Fig. 3.
Further research will concentrate on areas such as evaluation of metal gate electrode materials, different concepts to implement these metal gates, and the influence of the different process steps.
Better PEB temperature profiling
Engineers at SensArray, Fremont, CA, have developed a robotically loaded temperature measurement system with a 200mm or 300mm sensor wafer and attached self-contained wireless electronics formed in the weight of a silicon wafer (see photo).
This setup was designed to track transient and steady-state temperature profiles during post exposure bake (PEB). Initial testing in a production environment has demonstrated thermal detection capabilities exceeding the industry's targeted thermal requirements.
 The SensArray Accura??C instrumented wafer loaded into a PEB system. |
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"The nature of PEB hotplates — ~100mm proximity heating of sometimes 'cupped' wafers from non-flat hot plates, with the wafer often rocking on spacer pins — can create locally varying ramp times" that directly vary critical dimensions (CDs), said Mei Sun, speaking for the engineering group that also includes Barney Cohen, Farhat Quli, and Wayne Renken. "With the industry's tightening requirements for PEB control as a factor in controlling CDs to within 5.3nm (3σ) at the 130nm node, and 3.0nm at the 90nm node, the most accurate way to measure these dynamic temperature profiles in PEB systems is directly at the wafer, in real-time."
The systems' sensor wafer has embedded platinum resistance temperature detectors and a wireless intelligent sensor interface operating with BlueTooth RF wireless communications. It is robotically loaded and unloaded into a PEB chamber and moved through the system, and communicates to an external laptop computer.
After NIST-traceable calibration and testing on a uniform laboratory hot plate demonstrating a temperature accuracy of ±0.035°C, tests were performed in a production PEB chamber. Multiple runs were made to study the nature and rate of temperature change as the wafer was robotically loaded onto the PEB plate, lifted from the bake plate, and loaded onto a chill plate. "We found that the wafer stabilized on the bake plate 90 sec after the start of the ramp to bake temperature. The production PEB plate temperature range (1.022°C) exceeded the range observed on the laboratory uniform temperature hot plate, resulting from typical hot plate temperature nonuniformities and wafer to hot plate gap variations," says Sun.
According to the SensArray engineers, the temperature profile displayed two distinct regions during ramp up to bake temperature. In the initial 4 sec, the wafer temperature increased slowly because the wafer was on the lift pins in an up position, far from the hot plate surface. However, during the second ramp-up stage, the wafer was placed in close proximity (~100ηm) to the hot plate, causing an exponential rise to bake temperature.
"As CDs approach 5nm, understanding the impact of all process steps grows in importance. Metrology tools are required to supply more information, with greater accuracy. At the PEB step, this means high precision steady state and dynamic thermal measurements," added Mei Sun.
Expect brighter LEDs from this new process
A new process for growing gallium nitride (GaN) on a sapphire substrate should help with the fabrication of brighter green, blue, and white LEDs. The process — dubbed cantilever epitaxy — was developed at Sandia National Laboratories, Albuquerque, NM.
Sandia researcher Carol Ashby says, "Our new process eliminates many problems that have limited the optical and electronic performances of LEDs because the atoms of the two materials do not line up due to differences in lattice bond lengths, resulting in dislocations that limit LED brightness and performance."
The cantilever epitaxy process first forms narrow supports ("posts") by plasma etching the sapphire substrate to produce a striped post-trench pattern. A GaN nucleation layer is then grown on the sapphire posts at 500–600°C by metalorganic chemical vapor deposition; this nucleation layer helps bridge the crystal-lattice difference between the GaN and the sapphire.
 Figure 1. SEM of a cantilever epitaxy growth stopped before the cantilevers coalesce. |
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"At this point, a very key thing happens," says Sandia crystal grower Daniel Koleske. "First, at 950°C, GaN grows mostly upward, forming pyramids that reflect the crystal symmetry of GaN. When the temperature is increased to 1100°C, the pyramids grow laterally faster than vertically. This produces free-hanging cantilevers over the trenches between adjacent posts."
Eventually, the cantilevers meet over the middle of the trench and grow together, producing a continuous smooth surface held up by the narrow supports. The areas over the supports have very few dislocations when complete pyramids are formed during the 950°C growth step. When dislocations growing up from the post surface encounter the angled walls of the pyramids, they are turned from vertical to horizontal so they don't reach the surface as the material continues to grow thicker (Fig. 1).
There are some dislocations where two cantilevers grow together (the coalescence front), but almost no dislocations in the cantilever regions between the posts and the coalescence front.
The final result is a continuous smooth surface area with greatly reduced numbers of dislocations. This surface can then be used like a regular GaN substrate.
To support this work, Sandia researchers have applied TEM and SEM techniques to determine the amount of dislocations eliminated through the cantilever epitaxy process. "Looking at the material end on with TEM (Fig. 2)," says Sandia's David Follstaedt, "has shown that facets developed early in the cantilever growth process can turn dislocations very effectively when they are grown to full pyramids."
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Overall, the work at Sandia shows that the cantilever epitaxy process reduced the number of dislocations "to an order of a magnitude lower than conventional growth on planar sapphire," says Follstaedt. Ashby, Follstaedt, Christine Mitchell, and Jung Han (a former Sandian) have recently been awarded a patent for the cantilever epitaxy process. Substrates have been supplied to LED manufacturers for testing.
The cantilever epitaxy program at Sandia is part of an internal three-year $6.6 million Laboratory Directed Research and Development Grand Challenge. Funding for the program also comes from a grant from the Department of Energy Office of Building Technologies for a collaborative project with Lumileds Lighting.