An update on the status of wafer-level packaging
06/01/2003
Only a few years ago, wafer-level packaging entered the scene because it solved some of the dire needs in packaging, particularly the natural progression of chip scale packages (CSP), by moving conventional backend processing into the frontend. It even spawned two industry alliances of equipment suppliers and process developers — the Advanced Packaging and Interconnect Alliance (APiA) and the Semiconductor Equipment Consortium for Advanced Packaging (SECAP). Recently, we set out to gather a few views of wafer-level packaging's continued evolution and any technology hurdles that it faces.
Memory adoption
"What is driving this evolution may be up for some debate," says Stephen Kay, director of Advanced Packaging Technologies at Ultratech Stepper and steering committee member for the APiA. "Perhaps the biggest factor that will continue to drive wafer-level CSP will be its adoption into more mainstream applications, such as DRAMs. Outside of some analog devices and non-IC products, such as integrated passive devices and MOSFETS, chips that use wafer-level CSP have been mainly designed for a specific end product and therefore the adoption of a particular wafer-level CSP type was relatively limited."
 An interior view of Ultratech Steppers's Saturn Spectrum 300e2 FOUP system. |
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Kay explains that, driven by performance and form factor needs, DRAM adoption will necessitate continued infrastructure investment and bring in other equipment and materials companies, making wafer-level CSP more cost-effective. "It will also force some standardization in CSP package construction, I/O locations, etc. because DRAM is a 'commodity' that needs to be available in the same form from multiple sources," he says.
Dan Schmauch, director of advanced packaging at Semitool Inc., a SECAP member, adds, "Most wafer-level packaging to date has been at the extremes of device types — very low and very high end — for cost reasons in the former case and for performance reasons in the latter. But device performance requirements are increasing, and wafer-level techniques, as their volumes grow and processes are refined, must become cost-effective for more and more applications."
Schmauch adds: "Just prior to and into the first half of the present industry downturn, there was a very broad adoption of wafer-level processing for packaging, from traditional packaging subcontractors to foundries and IDMs, plus a few companies focused specifically on wafer bumping services.
 Semitool's electroplated solder bumps (pre-reflow) on a 300mm wafer. |
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"Since then, with penetration further along, plus continued lack of economic recovery, we now see the advanced packaging market generally tracking with the overall semiconductor industry and waiting for a strong upturn. What we have seen recently is heavily R&D oriented, with more focused efforts, not just a mad dash to avoid being left behind. Here, efforts fall into lead-free bumping, chip stacking, and cost reduction for expanded adoption," Schmauch says.
For ultimate wafer-level packaging, where die are packaged once a wafer is diced, wafer-level test could be a significant hurdle to adopting wafer-level CSP for mainstream applications. Kay says, "While performance and form factor gains are a driving force in wafer-level CSP adoption, the ability to fully test and burn-in a chip at the wafer level is key to the acceptance of wafer-level CSP."
While the challenges associated with lead-free bump processing can be viewed as an inhibitor, lead-free really is a side topic that has to be addressed for regulatory and consumer reasons, regardless of whether packaging is wafer level or not. Still, since most wafer-level packaging today is based on solder bumps, lead-free is one of those areas influencing adoption. "But I do not think this tendency is slowing the trend toward wafer level in any significant way," says Schmauch.
Other than memory
In one niche, for continued application of wafer-level CSP for applications with high I/O, Robert Mertens and Eric Beyne, IMEC, Leuven, Belgium, note that direct contacting between IC I/O pads and a PCB requires an IC pad pitch between 500 and 800μm to be compatible with standard PCB technology.
"This is in sharp contrast with increasing I/O pad density resulting from aggressive scaling and increasing complexity of ICs. Wafer-level solutions, such as wafer-level CSP, can reduce the IC ball pitch towards 300μm, but this technique will only be used for relatively large memory chips or low-pin-count chips," they say.
Work at IMEC envisions two solutions. First, a high I/O density IC can be interconnected to a standard PCB board using an intermediate "interposing" substrate — a high-density interconnect substrate that can translate chip geometries to PCB-level geometries.
"This way, IC pitches smaller than 100µm, even below 40µm, are targeted," say Mertens and Beyne. "Flip-chip interposer assembly is increasingly being done using wafer-level processing," they say.
Another approach uses bumpless packages, fabricated with wafer-level packaging, where the chip is embedded in another substrate, enabling a larger distance between the chips. The wafer-level CSP processes are then performed on this "reconstructed" wafer.
Within these two approaches and others, the message is that the industry must develop baseline process technologies that can be used for all different wafer-level packaging concepts. IMEC's approach has been in using its multilayer thin-film technology as the key enabling technology.
The IMEC engineers also see limits to the use of chip-sized wafer-level packaging because of compatibility requirements with standard assembly techniques and PCB technologies and the available infrastructure. The chips are simply becoming too small to connect them to boards with relaxed I/O pitch. An intermediate layer ("interposer") or a wafer "reconstruction" is therefore required to successfully apply wafer-level packaging techniques on the new "wafers."
For the future
Schmauch says, "Ultimately I see two primary drivers to increased evolution of wafer-level packaging: electrical-system performance and system packaging that is more in a smaller box. Both are enhanced by wafer-level packaging, and especially by advances in thin-wafer processing and die stacking. Enabling these are the increased availability, improving techniques, and reduction in costs of wafer-level packaging. Some of the costs are direct reductions, others must be viewed from a systems standpoint, for example, the cost-yield-performance of SoC vs. SiP."
"The market, while currently small, has the potential for substantial growth," Kay says. "However, the timing of full-scale adoption into mainstream applications such as DRAMs is still unclear." According to market research firm TechSearch International, wafer-level CSP will remain a fairly small portion, perhaps <2% of the overall packaging market through 2003. However, if DRAM packaging adopts this technology in subsequent years, growth beyond 7% of the overall market by 2005 is expected."
"I agree in general that wafer-level packaging will remain a very small niche in volume," says Schmauch. "On the other hand, I think we will continue to see rapid and broad expansion of wafer-level processing related to packaging. Just how much of that is considered BEOL vs. packaging isn't clear."
Pieter "Pete" Burggraaf, senior technical editor, Solid State Technology