Addressing mask costs
06/01/2003
Solid State Technology asked industry experts to provide insight on reducing the impact of rising mask costs.
Defect repair and photomask cost
David A. Lee, Roy White, RAVE LLC, Delray Beach, Florida, Brian J. Grenon, Grenon Consulting, Colchester, Vermont
 David A. Lee |
Perhaps one of the most contentious comments made in lithography circles this last decade has been that "there is no business case for mask repair." As a result, mask defect repair has not received a level of attention comparable to other maskmaking segments. Yet, as low-k1 lithography remains dominant and aggressive shrinks continue, the most difficult challenge in mask manufacturing is producing a mask without printable defects.
 Roy White |
When pattern generation times were 1–2 hours and pattern generators cost $4–5 million, it was more cost-effective to rewrite the mask than repair it; this is no longer the case. On complex masks, pattern generation times tend to be >12 hrs and final manufacturing yields are < or ~30% [1]. The cost of today's advanced mask pattern generation system can exceed $16 million. In an environment where recovery of development costs for maskmaking equipment is uncertain, improving yields is the primary way to reduce mask costs.
 Brian J. Grenon |
In a recent study, data indicated that yield has a larger impact on mask cost than capital equipment cost [2]. (It was assumed that capital equipment costs are ~$70–80 million, depreciated over five years.) Any process steps or equipment put in place to improve yields will have a positive effect, provided equipment cost is reasonable. To determine the effect, it is important to understand the specific value that a mask has at the point of introduction of the capital equipment or process step.
 Figure 1. Estimates of mask value as a function of 100, 50, and 33% yield before repair. |
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Figure 1 provides the estimated value of a 130nm alternating aperture phase-shift mask (altPSM) through the steps leading to repair. (The 33% case is aggressive, but reflects current conditions.) In a "real" mask-manufacturing environment, an altPSM mask has a "cost-only" value >$70,000. While increased complexity and extended mask pattern generation times have significantly affected cycle times, the largest effect is lower yields. Typically, an acceptable cycle time for a mask build is 1.5–2¥ the raw process time (RPT). RPT is the time required to manufacture a mask based on estimates of the time for each process step, not including queuing time or time spent waiting for a subsequent operation.
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Because mask delivery time is a function of RPT, yield, proficiency of the manufacturing line, line loading, and capacity, having robust defect repair capability increases yield and reduces cycle time, thereby increasing line capacity (Fig. 2). Significant cost savings can be realized through higher yields generated by a robust mask repair capability; comparing the difference in added value between a 33% and 50% yield when the mask arrives at repair, the estimated cost savings are approximately $22,000 (Fig. 1). In Fig. 2, it is seen that when the manufacturing yield is improved from 33% to 50%, a 30% reduction in cycle time can be realized.
Nanomachining — a combination of the positional control of an atomic force microscope (AFM) with a nanomachining head — provides a solution to yield and cycle time challenges. Using the technique, material can be removed at nanometer levels, and operations that present significant repair challenges — quartz bumps on altPSMs, trimming of carbon patches, removal of unknown contaminants, and repairs within tight lines and spaces — can be accomplished.
A repair of production-level alternating and embedded phase-shifting masks, as well as the ability to remove any foreign material on any base material with 5nm z-control has already been shown using nanomachining in several manufacturing operations — effectively removing existing roadblocks to photomask development. The technology readily repairs binary, attPSMs/altPSMs, as well as removing unknown contaminants from surfaces, offering greater impact/ dollar spent.
References
1. W.J. Trybula, K.R. Kimmel, B.J. Grenon, "Financial Impact of Technology Acceleration on Semiconductor Masks," 21st Annual BACUS Symposium on Photomask Technology, Editors G.T. Dao, B.J. Grenon, Vol. 4562, pp. 321–328, 2002.
2. R. White, M. Verbeek, R. Bozak, M. Klos, "Use of Nanomachining as a Technique to Reduce Scrap of High-end Photomasks," 21st Annual BACUS Symposium on Photomask Technology, Editors, G.T. Dao, B.J. Grenon, Vol. 4562, pp. 213–224, 2002.
For more information, contact David A. Lee at [email protected].
Intel's two-pronged approach
Chiang Yang, Barry Lieberman, Intel Mask Operations, Intel Corp., Santa Clara, California
 Chin Yang |
The mask industry is entering the most critical period in its history. The technical challenges are unprecedented as the burden of achieving the semiconductor industry roadmap cannot be lightened by timely reduction of exposure tool wavelength, but requires the fabrication of ever more complex masks. Meanwhile, the R&D funding required to sustain the mask capability roadmap has skyrocketed and the resources needed to operate a mask shop have become prohibitively expensive for many companies. The result is a major change in the landscape of the mask industry, with the formation of many alliances and a decline in the number of captive mask shops. These trends have further reduced the mask R&D base and put in jeopardy the continuation of the ITRS.
 Barry Lieberman |
In response, Intel is taking a two-pronged approach. First, we continue to invest in our captive mask shop. While fully recognizing the difficulties the mask industry is facing, Intel also views the situation as a great opportunity to increase differentiation from its competitors that do not have internal mask capabilities. An internal mask shop provides the following advantages: leading-edge mask capabilities, fast delivery cycle time, and cost containment.
By dedicating resources to address very specific internal customer needs, Intel can push the mask technology envelope well beyond the more general-purpose solutions that merchant mask shops typically provide. Additionally, the speed of mask delivery is critical to the success of the semiconductor business due to the rapid decline of the average selling price of ICs. An internal mask shop offers advantages in streamlined procedures and efficient coordination, leading to lower costs. By not being burdened by profit margins, an internal mask shop further provides a significant advantage in the early stages of silicon processes or new product development when iterations of test masks or product-stepping masks are extremely important. These masks can be generated with incremental variable costs in a captive mask shop, while full prices need to be paid if ordered from a merchant shop. Of course, this is only true if the ultimate volume justifies the capital expenditure for having the mask shop in the first place.
A second approach needed to address the challenges of mask technical difficulties and R&D funding gap is to increase collaboration and pooling of resources within the industry. In selected areas, Intel has entered into joint development programs with mask equipment or materials suppliers, as well as with other mask shops to enhance capabilities. Intel has also been very active in supporting the mask infrastructure through consortia-funded programs. The many consortia in which we participate include MARCO, SRC, and ISMT in the US, IMEC in Europe, and ASET and MIRAI in Japan.
A healthy mask infrastructure with a strong equipment and materials supplier base provides the foundation for making the advanced masks needed to meet the silicon technology roadmap, and this is the area of greatest concern due to the widening R&D funding gap. More creative collaboration within the industry, especially in the pre-competitive phase of R&D activity, is urgently needed. Still, all the resource pooling within the industry will not fully close the funding gap — external support may be required.
Intel has been participating in the discussions initiated by US merchant mask shops to form a mask-focused forum or consortium. The main objective of this proposal would be to secure government funding for research institutions and mask infrastructure companies (mask equipment and materials suppliers).
For more information, contact Chiang Yang, [email protected].
Maintaining design hierarchy key to faster turn-around-time
Steffen Schulze, Mentor Graphics Corp., Wilsonville, Oregon
 Steffen Schulze |
Looking to the next generation of ICs at the 65nm node, data preparation and mask-manufacturing communities are increasingly concerned with the complexity of the data-.handling flow. Since the closure of the gap between target feature size and exposure wavelength is not yet in sight, increasingly aggressive resolution enhancement techniques (RETs) are being deployed to achieve required feature sizes. Complex pattern treatments and mask layer splitting, as in the case of phase-shifting masks, combined with growing design density, create increased data volumes. The International Technology Roadmap for Semiconductors (ITRS) predicts file sizes will reach 100Gb this year. This seriously impacts throughput and mask turn-around-time (TAT).
Rethinking the mask data preparation (MDP) process is critical to mask-manufacturing efficiency. MDP includes geometry-processing steps (such as Boolean operations, sizing steps, and generation of manufacturing aids [e.g., dummy fill]), export to mask-writer formats, reticle layout and, mask rule checking. The traditional export process converts (or fractures) the open, standard hierarchical design data to a proprietary, intermediate format of flattened data. This flattened data is later converted into the format specifically required for the various types of mask-writing equipment. But commonly, MEBES (electron beam machine) data is generated even if the mask will later be built on a variable shaped beam (VSB) machine such as JEOL, Toshiba, Hitachi, or Leica.
This standard of multistep reprocessing complicates matters. Not only is the input format flat, which results in longer processing time, but the capability of utilizing the hierarchical constructs of the VSB formats is also limited, resulting in large file sizes — and big files create big problems.
While data preparation on large data sets can easily take days, a major contributor to TAT is the mask-writing process itself. The data volume bottleneck is not only triggered by the individual file size, but also by the distributed nature of the data preparation flow. The flow concatenates many steps at different locations and in a number of tools that require archiving of intermediate data representations as the data is exchanged. If the data is flattened too early, any subsequent processing is less efficient.
Growing file sizes have an additional side effect: they greatly impact capital equipment utilization, as mask machines are hampered and work-flow management loses efficiency. Mask houses are eagerly seeking a solution, because the problem will only become larger as features get smaller.
Key to reducing the bottleneck is to contain file size at the export stage. This can be done by maintaining data hierarchy and preventing data from being flattened too early. If the file is hierarchy-preserved until just prior to reticle manufacture, the efficiency of hierarchical processing can be maintained throughout the flow.
Hierarchy-based MDP tools enable geometry-processing steps far more efficiently when processed in open standard hierarchical design formats, such as GDSII. Any subsequent processing that may be required can still leverage the hierarchy present in the data. When hierarchy is preserved and the GDSII layout data is directly converted into the final mask-writer format, the amount of exported data shapes and data volume is minimized, enabling fast mask-write times. If the final mask data is created directly for the hierarchical database, output file size can be reduced up to 30% and processing time can realize a speedup of 6¥.
Adopting this new methodology can facilitate a single, continuous flow from tape-out to mask-writer, eliminating the need for intermediary interfaces and multiple transformations of the data. This makes data management much easier and can result in overnight TAT.
There are secondary and equally important benefits. This methodology can streamline work flow within the mask house and increase equipment utilization by enabling mask-writers to maintain performance, even as gate count and design sizes continue to grow as predicted by the ITRS.
For more information, contact Steffen Schulze, ph 503/685-0154, fax 503/685-1239, e-mail steffen_schulze@ mentor.com.