Integrating high-k dielectrics: etched polysilicon or metal gates?
06/01/2003
Overview
There is an immediate need for reduced gate leakage/higher capacitance gate stacks for stand-by low power applications. For high-performance applications, where leakage is less of a restraining factor, the motivation for the introduction of high-k dielectrics predominantly comes from the manufacturability difficulties of sub-1.0nm SiO2-based dielectric layers. In response to these challenges, conventionally etched HfO2-based polysilicon and TaN-gated NMOS devices, featuring gate lengths down to 65nm, have been fabricated, and functional HfO2-based transistors, both with polysilicon and metal gate electrodes, have been demonstrated. The results showed the viability of etching high-k dielectric gate stacks in a single chamber using standard processing equipment.
For rapid introduction of high-k materials into current CMOS platforms, compatibility of the dielectric layer with conventional polysilicon gate electrodes is critical. However, inferior leakage behavior, yield reduction, and threshold voltage instability for HfO2/polysilicon devices has been reported. Therefore, an alternative under consideration is the introduction of metal gate electrodes. These are also beneficial for aggressive equivalent oxide thickness (EOT) scaling since there is no impact on the capacitance equivalent thickness (CET) due to polysilicon gate depletion.
The complete change of the gate stack (i.e., gate dielectric and gate electrode) also significantly impacts the integration challenges for 65nm and below CMOS technologies. Specifically, at the gate stack patterning level, innovative approaches are required to fabricate either polysilicon or metal gate etch on high-k dielectrics as well as selective high-k removal from source and drain areas. In this development work, conventional HfO2-based NMOS transistors were manufactured, both with polysilicon and metal gate electrodes, and performance of both devices was compared.
Besides eliminating the problem of polysilicon depletion, the metal gate transistors that were made for this study achieved better performance when compared with identical HfO2-based dielectrics. Improved EOT and CET scaling performance and 2x the drive current value were also attained. The high-k insulating metal oxides that were evaluated provide the required specific capacitance, achieving lower leakage, at a considerably larger physical thickness for use in novel gate dielectrics for silicon MOS devices as opposed to SiO2.
Transistor preparation
Etched self-aligned NMOS transistors with gate lengths down to 65nm using an identical HfO2-based dielectric stack were prepared with both polysilicon and TaN gates. The polysilicon transistors were manufactured with a conventional self-aligned transistor flow and measured after silicidation using a dedicated mask set that allows electrical measurements on silicide [1].
 Figure 1. X-SEM image of the 100nm encapsulated HfO2/TaN/TiN gate stack after spacer etch. |
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The manufacturing of the TaN-gated transistors is also based on a conventional integration scheme with the exception of the introduction of a fully encapsulating spacer (Fig. 1), which is required to avoid dissolution of the metal gate during the silicidation process. To achieve the gate encapsulation, the hardmask used for the gate etch was not removed and thus provided the top cap of the encapsulating spacer. The TaN gate electrode is only 10nm thick, which is sufficient to define the work function [2]. Therefore, we opted for a double metal stack, consisting of a 10nm TaN layer (work function ª 4.3 eV) capped by a 70nm TiN layer. The capping material was chosen for its good barrier and thermal properties.
These transistors do not take all possible integration issues into account but are excellent test vehicles to evaluate gate stack etch development and high-k and gate electrode performance.
Patterning metal and polysilicon high-k gate stacks
The introduction of high-k dielectrics with conventional polysilicon or metal gates clearly presents important new etch challenges. The gate-patterning step requires the development of polysilicon and metal gate etch processes with selectivity to the underlying high-k material. In the integration route selected for this study, the gate-patterning step is followed immediately by the high-k removal step. In this process, the high-k material needs to be removed selectively to the underlying silicon substrate in the active areas, the SiO2 in the field areas, and the previously patterned gate material itself. Depending on the stack configuration, more specifically, with the presence of a hardmask or other sacrificial layers, the option of stripping the resist between the gate material patterning and the high-k removal exists.
The expected result of both steps are polysilicon or metal features with vertical profiles and tight CD control, no damage to the silicon substrate, minimal recess in the active area silicon and field oxide, and no high-k foot extending from the gate structures. The wafers should also be free of resist, residues, and redeposited high-k material. In this study, the gate patterning, hardmask etch, resist strip, and high-k removal processes were all done in situ in a 2300 Versys silicon etch system.
For development of the polysilicon process, existing Cl2/HBr-based chemistries used for conventional gate polysilicon etch were optimized for polysilicon gate etch on HfO2-based dielectrics. Using integrated interferometric pre-endpointing of the polysilicon main etch enabled switching to a more selective second main etch and over-etch, thus achieving high selectivity toward the gate dielectric. After etch and strip, no pitting, sidewall trenching, or other damage of the dielectric was observed. Obviously, the amount of HfO2-based material removed depends on the deposition technique and the anneal conditions, but is always significantly <0.8nm.
Alternatively, etching the metal stacks required optimizing a complete new process. The stack typically consisted of a 70nm oxide hardmask, 70nm TiN, and 10nm TaN on 3–4nm HfO2. The metal stack was etched using the oxide hardmask. This requires a resist strip after the hardmask open process. Instead of using interferometric pre-endpointing, the TiN and TaN were etched with a standard OES-based endpoint technique. Chlorine-based processes followed by a solvent clean were optimized, resulting in vertical profiles with good selectivity to the underlying high-k dielectric. No residues or polymers were detected on the wafers after inspection.
After gate electrode patterning, selective high-k removal is required. This implies minimal silicon recess, no damage of the patterned gate, and no high-k residues. Different high-k removal chemistries and strategies were developed for this step.
Minimizing high-k foot formation is another integration challenge. During gate patterning, passivating polymers may deposit on the sidewalls while controlling the profile. If these polymers are present during the high-k removal step, a foot is created — but this can be avoided by implementing a standard strip following gate patterning. Similarly, if the high-k removal process itself is polymerizing (e.g., to minimize recess), under certain conditions, a marginal high-k foot can be observed.
From a transistor performance point of view, it is important to minimize the silicon recess. Compared to conventional SiO2 dielectrics, high-k materials are more resistant to wet chemistries and require alternative removal strategies.
A very promising approach, consisting of a combined dry/wet removal of the high-k is in development; its main advantage is the virtually infinite selectivity to the underlying silicon. Any observed recess is attributed to the presence of an interfacial SiO2 layer underneath the high-k. Without optimization of this process, only limited selectivity to the exposed field oxide is achieved. Assessing whether this approach is compatible with all potential metal gate electrode materials requires further study.
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Another strategy relies on a dry-etch-only approach that requires chemistries that cause silicon chemical passivation or polymer deposition upon exposure of the silicon substrate, thus inhibiting further etching. Controlling bias voltage below the silicon sputter threshold further improves recess performance. Figure 2 shows a TEM picture of a typical result following polysilicon etch and dry high-k removal.
Based on the above developments, it appears that, with HfO2-based dielectrics, minimum recess can be achieved, irrespective of the current choice of gate material.
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Electrical evaluation
For the polysilicon-gated transistor evaluation, HfO2-based dielectrics were compared with nitrided SiO2 of comparable EOT value. Employing high-k reduced leakage current by approximately four orders of magnitude. The drive currents of the HfO2 transistors, however, were significantly degraded compared to the reference SiO2 transistors.
To compare the polysilicon and metal gated devices, an identical high-k gate stack was chosen. Selected transistor parameters and the high-k gate stack process conditions are reported in the table. The decreased difference between the EOT and CET values for metal-gated devices, relative to the polysilicon devices, confirms the absence of polysilicon depletion. It is generally accepted that the shift to a metal gate can result in reducing EOT up to 0.5nm. In this case, however, a 0.7nm EOT difference was observed between the polysilicon- and metal-gated devices, apparently indicating less interaction between the dielectric and the metal gate.
The table shows the threshold voltage, sub-threshold slope, peak mobility, and leakage at VFB-1V for the large channel devices. The Vth of the metal-gated and polysilicon devices is similar, indicating the appropriate work function of TaN. Taking into account the considerably lower EOT values of the metal-gated devices, the leakage level is acceptable compared to the polysilicon devices. The leakage increase with EOT scaling is similar to that of SiO2, but the absolute leakage levels are lower.
 Figure 3. IdVg curves for large channel polysilicon- and TaN-gated transistors (10 x 10μm devices). |
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Figure 3 shows the IdVg curves for the large channel devices. In general, an enhanced drive current is expected for decreased CET values. This explains, in part, why the drive current is higher for TaN-gated transistors for an identical high-k dielectric. However, the magnitude of the observed increase cannot be solely explained by this effect. The other contribution to the enhanced drive current is the increased mobility for TaN-gated devices, as indicated in the table.
Conclusion
The integration of new dielectric and gate materials critically depends on the availability and performance of gate stack etch processes. Suitable etch processes were developed in a single chamber using standard processing equipment, then tested in the manufacture of new devices. These conventionally etched high-k/.TaN-gated NMOS devices achieved CET values (~1.6nm) that fulfill the ITRS 2001 requirements for the 65nm high-performance node (25nm gate length) and 45nm low operating power node (22nm gate length). Employing metal-gated high-k stacks not only eliminated the gate depletion observed with polysilicon, but also improved EOT and CET scaling performance and drive current due to less interaction between high-k materials and the gate electrode.
Tom Schram, Stephan Beckx, Stefan De Gendt, IMEC, Leuven, Belgium
Johan Vertommen, Steve Lee, Lam Research Corp., Fremont, California
Acknowledgments
The authors thank G.S. Lujan, R.J.P. Lander, J.-F. De Marneffe, W. Deweerd, W. Boullart, S. Van Elshocht, P. Jaenen, Martine Claes, and the IMEC p-line for the valuable assistance during processing and measurement of the transistors and S. Ramalingam, G. Kota, and B. Coenegrachts of Lam Research Corp. for help with the etch process development. Versys is a trademark of Lam Research Corp.
References
1. R. Carter, et al., IEEE SISC 2002, San Diego, CA, p. 2, 2002.
2. T. Schram, et al., AVS Int'l. Conf. on Microelectronics and Interfaces, Santa Clara, CA, 2003.
For more information, contact Tom Schram at [email protected], ph 32/16-288-554, fax 32/16-281-214, Kapeldreef 75, B-3001 Heverlee, Belgium, or Johan Vertommen at [email protected], ph 32/16-281-860, fax 32/16-281-214, Kapeldreef 75, B-3001 Heverlee, Belgium.