Spin-on application of topside A/R coatings
06/01/2003
Overview
The use of aqueous-based topside antireflective coatings (TARCs) for the purpose of improving CD control is a common photolithographic process. The benefits of the CD control however, can be negated by yield losses due to the formation of defects in the spin-on application of the TARC. During the optimization of TARC, it is therefore important to consider defect counts along with target thickness and coating uniformity. This article will provide a look into the evaluation of current processes used in TARC application.
As feature sizes shrink, it becomes increasingly important to gain a better control of CD variation. A source of CD variation comes from the differences in reflectivity and absorption caused by variation in resist thickness as a result of topography. A common way for improving CD control by reducing interference effects is to create a topside antireflective layer [1, 2]. TARCs have been proven to reduce interference effects by reducing the reflectance at the resist/TARC interface, thereby reducing the swing amplitude.
In order to achieve the target coating thickness, maximize coating uniformity, and minimize defect counts, it is necessary to optimize the installation, spin-on application, environmental conditions, and equipment setup. In addition, data will be presented demonstrating the problems that occur when baking TARC and resist together.
Defect evaluation
One of the purposes of this project was to evaluate the defects associated with the spin-on application of TARC. Initial testing showed that the majority of defects were microbubbles. In order to accurately quantify defect size distributions, the metrology tool was calibrated with two polystyrene latex sphere deposition wafers. The first deposition wafer was made for measuring defects on TARC-coated bare silicon. The second wafer was made for measuring defects on a TARC
esist film stack. The optimized metrology recipe showed that 85% of the defects were <0.5μm.
Target thickness
The target thickness of the TARC used in this project was 440Å and was calculated by using Eqn. 1.
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where &lamda; (nm) = 248nm for a deep ultraviolet (DUV) process and nTARC = 1.41.
TARC installation
Defect reduction starts with the installation of the TARC. If the bottle has been shaken prior to loading, then bubbles are more likely to be introduced into the dispense lines. It was found that the introduction of bubbles into the line could be reduced by placing the TARC into the chemical cabinet of the CLEAN TRACK ACT 8, loosening the bottle cap to allow the bottle to vent, and then letting it degas.
The chemical line was first purged with enough deionized water (DIW) to remove any air in the line, pump, and filter. Purging was performed using N2 pressure on the DIW bottle and the purge function on the tool; the bubbles were removed without actuating the pump. After sufficient purging, the DIW in the liquid end tank of the tool was drained, and a bottle of TARC was installed. The same N2 purge function was then used on the TARC. Purging the TARC through the line without removing the DIW prevented the formation of bubbles that normally occur from purging a dry line. The thickness was checked in order to determine when enough TARC had been purged.
It was also found that daily purging of the pump helped reduce bubble defects and large coating defects. It is impractical to purge daily, but there is an ongoing investigation into new hardware, such as pumps and filters, that may lead to defect improvements without the hassle of purging.
TARC setup on bare silicon wafers
It is common practice for engineers to optimize new spin-on coatings on top of bare silicon wafers. As with all spin-on applications, however, setting up on bare silicon should only be the first step and results should be verified on top of the same substrate as that used in actual processing. The initial setup for the TARC was therefore done on bare silicon wafers in order to demonstrate the differences in how the process may change when applied to resist substrate.
The optimization of the TARC thickness and uniformity was conducted using the same procedure that would be used for any spin-on application. Adjustments to the dispense conditions, spin conditions, wafer temperature, TARC temperature, and environmental conditions were all considered. The first step was to determine whether to use a static or dynamic dispense. Since defect count was a major consideration, the type of dispense used would depend on which resulted in fewer defects.
Volumes of TARC ranging from 1.0–3.5ml were tested with static dispense. After dispensing on the wafer, the wafer was spun at a certain ramp speed. By increasing the ramp speed, less TARC was needed to cover the wafer, and at 50rpm and slower, all dispense volumes resulted in edge voids or other coating defects (Fig. 1).
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The same volumes were tested with dynamic dispense while the wafer rotated at speeds ranging from 500–2000rpm. All dynamic dispense trials had incomplete coverage of TARC. No testing was conducted at speeds >2000rpm due to target thickness constraints. For better coverage of the wafer using the same volumes at lower rotational speeds, a DIW pre-wet was attempted. The pre-wet involved dispensing DIW on the wafer and spinning for 0.1–1.0 sec before dispensing the TARC. It was found that complete coverage of the wafer was possible; however, the number of microbubble defects increased around the edge of the wafer.
In an attempt to increase the wettability of the wafer surface with the DIW, additional testing was conducted with a DIW pre-wet. There was no improvement in defect count or coverage from this testing. Overall, the dispense tests showed that static dispensing gave better defect count and coverage results than dynamic dispensing.
After determining a static dispense was necessary, the dispense conditions were optimized. Due to the ease of developing bubbles in the TARC, the dispense rate along with the dispense start and stop speed become important. During a static dispense, the faster the TARC is applied, the smaller the puddle will be before it is spread during the ramp step. If the TARC is dispensed too slowly, then the puddle forms irregular shapes that could affect coating uniformity.
Static dispense testing included dispense rates ranging from 0.5–1.0ml/sec. It was found that the dispense rate had no impact on the coating uniformity, but did have some impact on the defect count. The slower dispense rate had fewer defects and due to the nature of TARC, the dispense start-and-stop speeds were also slowed. Bubbles could be seen in the nozzle tip when starting or stopping the dispense too quickly.
Other bare wafer tests included changing the humidity in the TARC coating environment to determine its effect on coating thickness, defect counts, and wettability of the wafer. The humidity was decreased from 50% to 35%, but it was found that it had no effect on the defect count or the wettability of the wafer. However, there was a -4Å/%RH change across the range of humidity tested.
The coating recipe for TARC has four parts. First, a static dispense of TARC is performed. Second, the rotation of the wafer is ramped up in order to spread the TARC across the wafer. Third, the rotation or casting speed is held constant until the TARC coating is dry. This step is used to adjust the thickness of the TARC. The last part of the recipe contains an EBR (edge bead removal) and/or backrinse to remove TARC from the edge of the wafer. This step has no impact on coating thickness or uniformity if the wafer is completely dried during the previous (i.e., casting) step. From the results previously mentioned, the first step of the TARC coat recipe should contain a static dispense on the wafer at a rate of 0.5ml/sec.
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For the second step, results showed that the slower ramp speeds had lower defect numbers, but thickness and uniformity remained equal (Table 1). Defect counts were also evaluated by changing the amount of time the ramp step was executed; the ramp was increased from 2–8 sec. The shorter ramp steps had a tendency to have fewer defects.
 Figure 2. Spin curves. |
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 Figure 3. Results from optimized coating recipe. Top: coating profile; bottom: defect wafer map. |
The third step of the coating recipe is used to set the thickness of the TARC. Spin curves were produced in order to determine the casting speed needed to achieve 440Å for coating on both silicon and resist (Fig. 2). The spin curve for TARC on silicon shows that the target thickness could be achieved at ~1000rpm, and the spin curve for the TARC on resist shows that the target thickness could be achieved at ~900rpm. The difference in thickness between the two plots may be due to error in the model used on the measurement tool. For both spin curves, the target thickness is at a point on the spin curve where the standard deviation is high. The optimal spin speed on the curve is ~2000rpm, where standard deviation is at its lowest point. By increasing the viscosity of the TARC, the spin curve can be shifted to yield 440Å at ~2000rpm. The TARC profile from the optimized recipe is shown in Fig. 3.
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Once the optimum coating recipe was developed, other variables were altered to determine if improvements in uniformity and defect count were possible. To determine effects on uniformity, the TARC temperature was changed from 21 to 23°C. By varying the chemical temperature, the thickness of the wafer in the center can be raised or lowered except for the TARC — it had only a marginal effect on the center of the wafer (Table 2).
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In order to prevent a temperature gradient between the wafer and the coating environment, the wafer sits on a cooling plate that brings it to a set temperature before it is coated. Typically, the temperature can be used to improve the coating profile. The cooling plate was changed from 22 to 24°C to determine if the coating uniformity could be improved. While the cooling plate usually has a large impact on coating uniformity, testing showed that for TARC the influence was negligible (Table 3).
 Figure 4. Comparison of defect counts between baked and unbaked TARC-coated wafers. |
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The last test on bare silicon involved baking the wafer coated with TARC. The chemical vendor recommends two methods of TARC processing: 1) resist apply, post-apply bake (PAB), TARC apply, and 2) resist apply, TARC apply, PAB. Bare wafers coated with TARC were baked and compared to those not baked to determine which is a better practice. The results show that the wafers that were baked had almost 3¥ as many bubble defects (Fig. 4).
TARC setup on resist-coated wafers
Once the setup was optimized on bare silicon wafers, the process was transferred to a resist substrate. The same coating recipe used on bare silicon would not coat on resist due to the increased surface tension between the TARC and resist. The edge of the wafer had voids along the edge. The coating recipe had to be changed in order to get complete wafer coverage of TARC on top of the resist.
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It was determined that by increasing the ramp speed, it would be possible to get complete wafer coverage, but the TARC thickness decreased. Therefore, high ramp speeds were tested at very small increments of time in order to balance wafer coverage and TARC thickness loss. Once an optimal speed and time were discovered, they were rechecked on bare silicon. At a ramp speed of 1800rpm for 0.5 sec, it was possible to get complete wafer coverage on top of resist and maintain coating thickness and uniformity. Defect counts for TARC on resist were lower than those on bare silicon.
Baking resist/TARC
It is acceptable to bake wafers coated with TARC and resist; testing, however, shows that this may not be optimal for defect count or for maintaining exposed image profiles. When the PAB was performed after both resist and TARC were coated, the defect number was nearly doubled. Also, when baking the TARC and resist layer together, there was noticeable resist loss after developing.
 Figure 5. Bake test. |
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 Figure 6. Comparison between wafers baked at different lengths of time with TARC and resist and wafers with resist only. |
Testing was conducted to prove that the highly acidic component of TARC rapidly diffuses through the resist surface during the bake, making regions of the resist more soluble in the developer. Wafers were baked at different temperatures and at different lengths of time, and then were developed without being exposed. The results were then compared to wafers tested under the same conditions, but only coated with resist. There was a rapid decrease in resist thickness as the bake temperature increased for wafers coated with TARC and resist (Fig 5). The wafers that were baked without TARC had little resist loss after developing. The TARC and resist-coated wafers had increased resist loss when baked longer, compared to the wafers that were baked without TARC (Fig. 6).
 Figure 7. Wafer 1: no TARC; wafer 2: exposed, baked, and developed with TARC; and wafer 3: exposed with TARC, baked and developed without TARC. |
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A pattern test was conducted in order to see the effects of baking with TARC. The first wafer was not coated with TARC. The second wafer was coated with TARC, exposed, baked, and then developed. The third wafer was coated with TARC, exposed, rinsed to remove the TARC, baked, and then developed. This test was repeated for two different exposure doses. Results of the linewidth measurements are listed in Table 4. There is some line slimming on the wafers that were coated with TARC and then rinsed before baking, and considerable line slimming and top rounding on the wafers that were baked with TARC (Fig. 7).
Conclusion
Proper measures in the installation process of the TARC (e.g., allow bottle to degas, purge dispense line with DIW before pumping, slow start/stop speed for dispense valve, etc.) are necessary to reduce defects caused by microbubbles. Additionally, a slower dispense rate reduces bubble formation and static dispense is recommended.
Ramp speed controls the amount of TARC needed for complete wafer coverage — a slower ramp speed resulted in fewer defects. Short ramp times also had fewer defects. It was found that bare silicon recipes do not transfer well and changing the TARC temperature had a negligible effect on uniformity and defects. Similarly, changing the cooling plate temperature had a marginal effect on uniformity and no effect on defect counts. Humidity had no effect on wafer coverage, but thickness was affected. Baking with TARC on resist leads to increased resist loss, line slimming, and top rounding of the images. Baking also increased TARC defect counts. Testing showed that the viscosity of the TARC was not optimal for target thickness and uniformity. This resulted in a small process window for optimizing defects, and, therefore, the improvements were limited.
Brian Head, Tokyo Electron Texas LLC, Austin, Texas
Acknowledgments
The author would like to thank David Farlow for his assistance in running the experiments. CLEAN TRACK ACT 8 is a registered trademark of Tokyo Electron Ltd.
References
1. S. Miura, C. Lyons, T. Brunner, "Reduction of Linewidth Variation over Reflective Topography," Proc. SPIE, 1674, 10, 1992.
2. M. Gehm et al., "Evaluation of Methods to Reduce Linewidth Variation Due to Topography for i-line and Deep-UV Lithography," Proc. SPIE, 1674, 72, 1992.
Brian Head received his BS in chemical engineering from the U. of Texas. He is in the process engineering group at Tokyo Electron Texas LLC, 2500 Montopolis Dr., Austin, TX, 78741; ph 512/486-4218, e-mail: [email protected].