SPIE Microlithography Report: LIL may bridge 157nm, EUV gap
05/01/2003
Although there were mixed messages about an uncertain lithography future at the SPIE Microlithography Symposium in Santa Clara, CA, Feb. 23–28, it appears that immersion optics may save the day.
Nikon showed a revised roadmap, including immersion versions of both 193 and 157nm stepper/scanners along with SEMs of alternating lines at 90 and 65nm produced with immersion optics. No scattering from microbubbles or interactions between water and the resist, two major potential problems, were evident. If successful, immersion could provide a bridge to fill in for 157nm and EUV lithography, which are steadily progressing but still may not be ready to hit targets set in the latest roadmap.
Other highlights of the intense, five-day conference included: updates on progress in large-NA 193nm and dry 157nm exposure tools by Nikon, ASML, and Canon; innovative new concepts, such as digital holography for wafer inspection; improved chromeless phase litho methods; and lithography-friendly design schemes to improve chip layouts for applying reticle enhancement techniques (RETs).
Liquid immersion lithography
Experiments with liquid immersion lithography (LIL) have so far been very promising. Bruce Smith of Rochester Institute of Technology (RIT) suggested that immersion could allow 193nm ArF sources to offer an effective wavelength of 134nm through a 44% improvement in numerical aperture (NA). LIL at 157nm could offer a 17% improvement over dry litho, Smith suggested. For 193nm, DI water appears to be the best solution, offering no light absorption and a refractive index of 1.4 at 213nm, according to Alex Raub of the U. of New Mexico.
While there appear to be some problems in LIL, they represent "technical challenges, not barriers," according to Smith.
At a Shipley-sponsored panel the opening day, Chris Progler of Photronics prefaced his remarks about immersion litho by playing a high-pitched (2.4x speed) rendition of "Tiny Bubbles." Smith of RIT pointed out that air is very soluble in water, and any microcavity will cause microbubbles. Soichi Owa of Nikon suggested that it would be critical to degas DI water before injection into an immersion system. Mike Switkes of MIT's Lincoln Labs said that they saw no bubbles down to 0.5µm, but they must go smaller. Sematech has formed a Bubble Task Force to study this area.
Another potential problem is sensitivity to polarization. The TE image is better than the TM image for 193nm, so polarized light will be needed. The TM image is only good at one angle, according to Smith. Lines and spaces might be done in one direction or the other, but it will be necessary to decompose contacts for printing, he suggested. Polarization will also complicate RETs.
While it appears that 193nm resists are compatible with water, a top coating (not an ARC) might be needed, according to Smith. Contamination of the water is another concern. Alexander Wei of the U. of Wisconsin, Madison, showed various schemes for using jets to inject the fluid under the lens. Modeling showed that opposing jets do not fill uniformly, allowing microbubbles to form, so a single jet appears to be a better solution.
Nikon's schematic showed a water supply on one side of the lens and a recovery tank on the other side. Keeping the water moving will cut down on contaminants. Both ionic and nonionic contaminants can strongly affect light absorption and index, according to Switkes of Lincoln Labs. The water had little effect on the 193nm resist, however, and an AFM showed little change in surface roughness, he reported. For 157nm immersion litho, fluorinated polymers are highly oxygen-absorbent (this could double the weight), so the Lincoln Labs group is looking for alternate materials. Switkes said that they are building a 157nm immersion microstepper and hope to have it built by the end of this year.
Owa of Nikon suggested that ArF with immersion optics may be considered equivalent to 134nm lithography with a depth of field of 150nm for 45nm features using a binary mask.
Advanced litho tools
The session on advanced tools highlighted progress on "dry" 157nm and large-NA 193nm tools. The consensus was that materials — except for soft pellicles — were no longer a problem at 157nm. The first full-field tool — the ASML Micrascan VII — is up and running with 0.75NA and a 26mm x 32mm field, according to Harry Sewell. Jan Mulkins of ASML explained how that tool — and follow-ons employing higher NA and the Twinscan platform — would address 65nm challenges without immersion.
Hitoshi Nakano of Canon described the assembly and tuning of its 5X FS1 tool, which would be used as a test bed for the 4X FS2 production scanner. Two papers from Nikon described an off-axis 0.85NA catadioptric design (without the beam-splitter of the Micrascan) that Nikon claimed would work at 90wph with a 40W laser in 2007. Such a tool would pattern 60nm gates with a binary reticle and 35nm with a strong phase-shifting mask.
At 193nm, all three companies are producing ~0.85NA exposure systems with similar capabilities. Canon claims the highest throughput at 140wph for its FPA-6000-AS4. Itaru Fujita explained how the defocus budget of that tool was improved by accounting for everything including reticle sag, and the linewidth margin was improved by reducing stage vibration, etc. Tsuneo Kanda described performance including a 550nm DOF with a 6% attenuating PSM at 80nm. Jos de Klerk described the performance of the ASML Twinscan 1200B system, which features diffractive optical elements in an exceptionally flexible illumination system. The 0.68% dose uniformity allows 80nm isolated lines to be printed with 3nm variation (3s) and 60nm dense lines to be printed with 250nm DOF using dipole illumination!
Nikon countered with a claim that its manufacturing proces was now producing lenses with full-field aberration levels below 0.013l, which was what was needed for 10% CD control at 70nm. With an attenuated-PSM, that resolution could be achieved with simple annular illumination, according to Nikon.
In the hallways, however, there were rumors of major DRAM manufacturers abandoning 193nm lithography and using large-NA 248nm tools with phase-shifting masks instead. One company was said to have found 193nm exposure 3X more expensive.
Wafer inspection
Digital holography for wafer inspection was the topic of a presentation by Mark Schultze of nLine Corp., Austin, TX. By processing the pattern obtained by combining DUV light reflected from a wafer with a reference wave in a microscope, the FATHOM die-to-die defect inspection system extracts the phase and amplitude of the reflection, which highlights small topography variations even for high-aspect-ratio features.
Because the interference pattern depends linearly on the amplitude of the reflected wave, not on its intensity, very weak reflections (like those from the bottom of subwavelength vias) are sufficient for good diagnostics. Schultze showed as examples a single, partly opened 80nm contact that showed up as a bright spot on the display and a partial-height line extension in a complex poly pattern. The system was said to be capable of 1wph throughput.
Optical lithography
With shorter wavelengths seemingly delayed, the focus of the optical lithography sessions was on extending 193nm and 248 DUV methods. Stephen Hsu of ASML MaskTools described a full-chip implementation of double-dipole lithography at 65nm. DRAM patterns could be printed with a 300nm DOF and 10% exposure latitude, but generating the two complementary binary masks needed was not trivial. Controlling the flare on pairs of bright-field masks required grids of nonprinting scattering bars in clear areas, which were not easy to make. Logic-like designs required model-based OPC.
Ju-Hyung Lee of Samsung compared the performance of chromeless PSM (also called CPL) with other attenuated phase shift techniques for nodes after 100nm. He found that five characteristic DRAM patterns could be printed better using the CPL method. Off-axis illumination gave 400nm DOF for 80nm CDs. Remarkably, Lee reported a MEEF <1 for CPL as opposed to 5 for the high-transmission attenuated-PSM.
Interest in alternating phase-shift has also been revived, with Richard Schenker reporting methods of patterning dense, isolated, and semidense contacts at k1 = 0.35 using phase-shifted assist features as necessary. Unhappily, mask inspection is still not capable of capturing all printable phase defects, according to Schenker.
Michael Fritze of MIT's Lincoln Laboratory explored the limits of strong phase-shift, placing them at 45nm for DUV, before resist shrink or process trickery. UV-baking appropriate resist shrinks both the CD and line-edge roughness, allowing 10nm final gate dimensions, according to Fritze. Test alt-PSMs have been printed at 157nm now, but at 15x magnification. That large factor allows the 90nm dual undercut needed to suppress focus-dependent space-width variation, resulting in a 150nm DOF at 70nm, according to Yung-Tin Chen of TSMC. On a poster, Yasutaka Morikawa of DNP showed how the same result could be obtained with fully supported chrome in a SCAA mask.
Design and process integration
More lithography-friendly chip design has long been desired by fab workers. Two symposia — one on design and process integration and the other on cost and performance in IC creation — attempted to address those desires. A joint session with the optical lithography meeting attempted to quantify the opportunities and costs. While Neil Berglund of the Oregon Graduate Institute clearly pointed out the evidence for increasing yield loss due to intradie problems, no magic bullet solution appeared likely.
 Layout optimization would allow more useful information to be transmitted into the resist through reduced detail. |
null
Lars Liebmann of IBM described the need for layout optimization. Near the limit of resolution, only grating-like structures will print reliably, and so the circuit topologies need to be redesigned to conform to this lithography rule, according to Liebmann. Loss of density is not inevitable, but the key measure of density is the contacted gate pitch, not the minimum pitch.
Liebmann advocated optimizing systems and designs around that concept, allowing more useful information to be transmitted into the resist through reduced detail (see figure). A properly laid-out chip can be coded for strong phase-shift or decorated with SRAFs easily, depending on the masking paradigm. "Enlightened design is a lifestyle choice, not a set of layout restrictions or design rules," advised Liebmann.
Sean O'Brien of Texas Instruments described the difficulty of applying RETs to real-world circuits. An OPC system with subresolution assist features may have a 1ppm failure rate, but with 60 million features/chip, those failure sites must be found and corrected before the design reaches manufacturing. That requires a 6s process with millions of test sites and complex sifting. TI has developed such a system capable of automated electrical test. The information is then used to refine the actual OPC method by eliminating marginal cases.
Still, errors occur; contact holes with assist slots can be placed close enough that the slots coalesce optically and print. To find them, O'Brien advocated exploiting the computer power available on idle PCs on a network. He proposed a new gridcomputing system: "OPC@home, the search for intelligent corrections."
Cost and performance in IC creation
Alfred Wong of the U. of Hong Kong pointed out the advantage of redesigning standard cells to put contacts on a grid. With such placement, the grid spacing might be reduced, but the kind of catastrophe reported by O'Brien could not happen. Advanced litho techniques like IDEAL SMILE would also increase yield.
The odd thing is, according to Wong, existing designs have peaked distributions of contact spacings and little change is actually required. The electrical performance is not notably degraded in simulations and the net circuit size can actually be reduced 2% by regularizing the contact spacings and applying advanced lithography.
By M.D. Levenson, Bob Haavind, Solid State Technology
The $6 million mask set
The reticle and photolithography working groups of SPIE held a joint panel discussion moderated by Klaus-Dieter Rinnen of Dataquest on "The $6 Million Mask Set — Truth and Consequences." Rinnen predicted that mask industry revenue would continue to be about 1.5% of semiconductor revenue, but a set of 30 masks for the 30nm node would cost $6 million in 2011 unless a new business model was found.
That price seemed both outrageous and plausible to panel members. For example, Marcus Dilger, manager of the new Advanced Reticle Center in Dresden, pointed out that his state-of-the-art facility cost 250 million euro and would produce only 7000 plates before it had to be replaced as obsolete. That corresponds to an amortization cost of $35,000/mask and a 30-reticle set of today's ~100nm state-of-the-art masks would then cost over $1 million in amortization alone, with no provision for labor, interest, taxes, profit, or any of the other costs of doing business.
Bob Leidy of IBM suggested that the increase in mask cost was due to increased pixel count, so a nine-fold increase (due to shrinking from 100nm to 30nm) would make Dilger's $1 million mask set worth $9 million, but it would cost less because the learning curve always drives costs down. In spite of all the whining, new captive mask fabs are being opened and proving their value to major manufacturers.
Barry Lieberman of Intel predicted that the industry would bifurcate into leading-edge companies with their own mask shops and everyone else, who would buy commodity masks from merchant vendors.
Neal Callan, LSI Logic, noted that Sematech estimated the median production run was 100 wafers and typical ASIC runs were about 9. Paying $6 million for a reticle set would put companies like his out of business, since about 70% of reticles required "re-spin" because of defects or errors. Maskless lithography might be a solution, said Phil Ware of Canon, but others argued that the space required to house enough 1wph e-beam machines to meet demand would be prohibitive. Ware suggested the direct-writers would not be aimed at high-volume fabs.
Nayoya Hayashi, a 25-year veteran of the merchant mask business representing DNP, explained how mask production costs rose 45¥ since the 500nm node, but prices rose only 25¥. He proposed a new production model using large re-used IP blocks in an advanced photo-repeater. That machine would allow ~6 master reticles to be patterned cheaply at 16x resolution and stitched together optically to form the final mask.
Ken Rygler, former executive VP of marketing and strategic planning at DuPont Photomasks, then pointed out mask industry revenue was once 5% of that of the semiconductor industry and both thrived. More recently, the mask people have not recovered their capital costs, leading to a decline in capability. Unless a new business model is implemented in which masks are treated as capital equipment and amortized — or mask houses are paid royalties on chip sales — the industry will continue to decline.
"The $6 million mask set is a financial problem with a financial solution, not a technical one," summarized Rygler.