Near speed-of-light velocities for on-chip transmission of electrical signals
05/01/2003
Using a design that takes advantage of the inductance-dominated, high-frequency regime of on-chip interconnect, comparable or better performance than proposed on-chip optical interconnects is possible without the additional associated manufacturing challenges of on-chip optics. The design is capable of transmitting data at velocities near the speed of light and offers a 5¥ improvement in delay over a conventional repeater-insertion strategy. An overall delay of 283psec for a 20mm-long line, corresponding to a propagation velocity of one half the speed of light in silicon dioxide, has been demonstrated in 0.18µm, 6-level aluminum CMOS technology.
Interconnect has long been perceived to be a bottleneck in present and future high-performance digital ICs for its inability to keep pace with advances in transistor speeds [1]. Alternative solutions such as on-chip optical interconnects have been proposed in order to avoid the problems associated with global on-chip wires altogether [2]. Due to technology incompatibility, cost considerations, and non-negligible delays in converting the signals between optical and electrical domains, this has not yet been shown to be practical. In this article, the velocity limitations for systems built with conventional silicon processing are explored; it is shown that data transmission at near the speed-of-light is possible in an all-electrical system.
Repeater insertion limitations
The most common means of global communication is through wires with appropriately spaced repeaters [3], which regenerate the signal at regular intervals to facilitate transmission. In 0.18µm, 1.8V CMOS, 6-level aluminum interconnect technology, the optimized minimum delay, including wire and buffer delays, is about 1.35nsec for propagation over a length of 20mm. This translates into an effective velocity of about one-tenth of cox, the speed of light in silicon dioxide. These simulations were carried out in HSPICE for minimum-width (0.44µm), minimum-spacing (0.46µm) lines [4].
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 Figure 2. Measured eye diagram for 2Gb/sec input signal across a 20mm wire. |
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While the buffer delays can be reduced by using more advanced device technology, the intrinsic wire delay is a function of the materials used. The introduction of copper and low-k dielectric materials improves the performance of these on-chip interconnects. These newer materials, however, are increasingly difficult to integrate into manufacturing processes, and the wire delays are still much slower than the time of flight, which is set by the speed of light.
By examining this signaling methodology, its limitations can be understood. The wire frequency characteristics are compared with the power spectral density of a 500psec digital pulse in Fig. 1 (blue curves). Conventional digital signals are broadband, and typical wire characteristics are such that different frequency components of the signal travel at different speeds. For transmission line systems, the phase velocity, rather than the group velocity, is meaningful to consider [5].
At lower frequencies, the wire behaves as a distributed resistance-capacitance (RC) network and the phase velocity increases linearly with frequency (at lower frequencies), until it saturates in the high GHz regime. In this RC regime, signals travel slowly by diffusion and undergo frequency dispersion. As the frequency increases, the inductive component of the wire dominates the resistance, and the wire behaves as a waveguide. The high-frequency, inductance-.capacitance (LC) regime allows for propagation of an electromagnetic wave. Thus, the peak phase velocity is the speed of light in the dielectric surrounding the interconnect, which can be exploited to achieve high-speed signal propagation.
Exploiting the LC nature of wires
A system that transmits signals at the speed of light can be achieved by taking advantage of the wave nature of the interconnect. At the same time, it is beneficial to eliminate the low-frequency portion of the signal that lags behind and contributes to intersymbol interference (ISI), when one data bit in a signal extends beyond its allocated clock cycle and adds noise to subsequent bits [6]. This new system can be achieved by modulating the digital data with a sufficiently high-frequency carrier, thus shifting most of the signal up into the faster LC regime (Fig. 1, red curves).
For this system to be realizable, wires must have a low crossover frequency between the RC and LC regimes. By emphasizing the parasitic inductance and reducing the resistance, this transition can be shifted into the single GHz range. The design strategy of deliberately using the parasitic inductance may be foreign to designers, since the inductance for on-chip wires is often difficult to estimate. In this case, the on-chip transmission lines have explicit ground returns that provide well-controlled and predictable inductance values.
While the high-frequency LC regime offers high-speed, frequency-dispersionless propagation, the interconnect is more lossy at higher frequencies. Therefore, thicker top layers of metal and dielectric facilitate the realization of on-chip transmission lines [7, 8]. Using an optimized interconnect lowers the crossover frequency between the RC and LC regimes to a few GHz (Fig. 1). Then, modulating with a high-frequency carrier pushes the signal spectral components to lie predominantly in the high-speed inductance-dominated region.
Sending signals at light speed
A simple implementation of this system uses direct conversion from baseband to RF — a 7.5GHz carrier — and a 0.18µm standard logic CMOS technology with 6 levels of aluminum/silicon dioxide interconnect. The transmission line is a differential microstrip with a 1µm-thick, 16µm-wide signal line over a 2.1µm intervening SiO2 layer. The delay of the system is 283psec over the length of 20mm with a power consumption of 16.1mW, supporting a bandwidth of 2Gb/sec. This total delay not only includes the time of flight across the interconnect and the transmitter and receiver delays, but also corresponds to an effective signal propagation speed of nearly one-half of cox. A sample eye diagram is shown in Fig. 2.
Comparisons with optical
On-chip optics promise speed-of-light transmission without the frequency dispersion and loss associated with electrical wires [2]. For viable on-chip optical interconnects, however, an integrated method of transforming signals from electrical to optical domains and back is necessary. Detailed simulations have been performed that quantify the delays due to the transformation overhead [9]. Overall delays range from 300–400psec for 20mm, depending on the optical source and optical waveguide used [10]. In terms of delay, the modulated signaling approach over electrical wires performs as well or better than the on-chip optical links. At the same time, the cost of thicker dielectrics and metal wires to support faster electrical propagation is well understood, while the cost of packaging and integrating optical transmitters, detectors, and/or waveguides is ominously unknown.
Conclusion
By using the techniques described, the performance of electrical wires can be enhanced to offer near speed-of-light, on-chip signal transmission without prohibitively expensive on-chip optics. While the ideas described have been applied to on-chip interconnect systems, it may also be possible to apply these techniques to chip-to-chip interconnect systems because of the nondispersive nature of the signals. Furthermore, there is a potential power savings from using high-frequency, narrowband terminations, instead of ones at DC that can contribute considerable static power dissipation.
By Richard T. Chang, S. Simon Wong, Center for Integrated Systems, Stanford University, Stanford, California
References
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4. R. Chang et al., IEEE J. of Solid State Circuits, accepted for publication.
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8. A. Deutsch et al., "When Are Transmission-line Effects Important for On-chip Interconnections?" IEEE Transactions on Microwave Theory and Techniques, Vol. 45, pp. 1836–1846, Oct. 1997.
9. E. Kyriaskis-Bitzaros et al., "Realistic End-to-End Simulation of the Optoelectronic Links and Comparison with the Electrical Interconnections for System-on-Chip Applications," Journal of Lightwave Technology, Vol. 19, pp. 1532–1541, Oct. 2001.
10. R. Chang, "Near Speed-of-Light On-chip Electrical Interconnect," PhD dissertation, Stanford University, 2002.
For more information, contact Richard T. Chang, c/o Prof. Simon Wong, Stanford University, CIS 202, MC 4070, Stanford, CA 94305-4070; e-mail [email protected].