SST editors ask industry experts about advanced wafer-cleaning evolution
05/01/2003
Considering that wafer cleaning is crucial to virtually every wafer-processing step, Solid State Technology asked several industry process experts: How do you perceive conventional wet chemistry or nonliquid wafer-cleaning technology evolving to meet advanced requirements for interfaces and particle control?
Array of challenges
Brian Kirkpatrick, senior member technical staff, silicon technology development, Texas Instruments, Dallas, Texas
 Brian Kirkpatrick |
With sub-90nm technology nodes, several new challenges are becoming apparent for surface preparation. Three of the most significant are high-efficiency particle cleans with no etch component or a much-reduced one when fragile structures are present (which I address in more detail below); cleaning trenches and vias with an easily damaged porous ultra-low-k dielectric exposed; and truly understanding and then controlling required defect densities on the wafer bevel and backside. As has been the case in the past for surface preparation, solutions to these challenges do not tend to converge on any one technology.
Within these three areas, the first is the most far-reaching surface preparation technology gap in the foreseeable future. If cleans remove significant amounts of silicon or oxide, impact can be measured at numerous locations throughout the process flow.
For example, shallow trench isolation recesses along the trench edge potentially leading to polysilicon stringers; gate poly pattern problems from focal plane differences; field channel stop breakdown caused by laterally forming silicide along the trench wall's top edge; drive current variation caused by changing the effective channel length by etching the sidewall of the polysilicon in the LDD/MDD loop; or variation in surface doping of the drain extensions caused by a variation in consumption of the substrate silicon and along with it the dopants, not to mention the impact on Gdl or Cgd, etc.
To fully understand the magnitude of the issue, one must define "without reliance on a significant etch component." Recent discussions of the surface preparation group for the 2003 ITRS update indicate thermal oxide loss needs to be below 1Å for the most critical processes at 90nm and below 0.5Å at the 65nm node. These values are versus a standardized test method, which uses undamaged thermal oxide, enabling accurate comparisons and benchmarking. Actual loss on the product wafer surface will be larger than this.
Solutions are likely to be as widespread as the impact. No single best solution is rising to the forefront, which may drive further market segmentation for tool types and configurations. This in itself is a paradigm shift for surface preparation. In other process disciplines, such as plasma etch, it has been accepted for multiple technology nodes that each individual process step will have a tool fully optimized for an individual step, ignoring other steps. For the most part, surface preparation has not done this.
At the 90nm node, the <1Å thermal oxide loss challenge can be met by optimizing process chemistries for the most part within existing tool sets. Some switching between immersion and spray is likely, but no fundamental gap is perceived. However, at the 65nm node challenge for <0.5Å, a fundamental gap is perceived. The most critical area in the process flow is also where one of the most fragile structures is exposed — the gate stack at drain extension process point.
Technology changes required for success must take into account oxide-silicon loss, not damaging fragile structures, and achieving acceptable defect densities. This makes the application of conventional megasonic cleaning problematic. Step-by-step trade-offs between the incoming cleaning challenge, such as fragility of the surface, how much oxide or silicon can be consumed, and which films are exposed, will be played off against the wafer surface cleanliness. The question is, how to provide sufficient energy to overcome van der Waals forces without reducing the surface contact area (etching), or pushing the particles off the wafer surface using cavitation bubbles (megasonics).
Technologies that bear watching all share one characteristic: a new way to apply mechanical force that does not depend on conventional megasonics. Options include off-axis megasonics, new DI water-rinsing techniques, aerosol jet scrubbing, supercritical CO2 (SCCO2) schemes that pulsate between supercritical and gaseous states, cryogenic aerosol, and electro-hydro dynamics.
The success or failure of each technique depends on how wide the process window is and how easy it is to optimize the force applied per process step. Wider process windows directly translate into a reduced number of total process recipes and fewer yield loss excursions. At all of the major semiconductor companies, independent of which method is used, critical process experimentation is underway that is attempting to reach these levels of oxide and silicon loss.
Si-dielectric interface key
Joel Barnett, project engineering, advanced gate cleans;
Naim Moumen, project manager, advanced gate cleans;
Robert W. Murto, program manager, advanced gate stack;
Howard R. Huff, senior fellow, International Sematech, Austin, Texas
As the industry evolves toward equivalent oxide thicknesses (EOT) approaching ≤1nm using high-k dielectric materials, there will be greater emphasis on the silicon-dielectric interface and its interaction due to subsequent thermal processing.
 (L to R): Murto, Barnett, Huff, Moumen |
For low standby power applications, where leakage current density is the major issue, the EOT can be a little thicker (1.5nm), although this may require the formation of a very smooth and controlled chemical oxide. The chemical oxide needs to be robust enough to function as part of the gate dielectric system.
One technique for achieving a thin, controlled chemical oxide might be through the use of ozonated-water clean processes. The chemical oxides that result from standard RCA-type cleans are generally too thick (in the case of SC1-SC2) or not of high quality (in the case of SC2 only). Ozone oxides can be controlled to one, two, or three monolayers of silicon oxide in thickness (three monolayers comprising a fully terminated chemical oxide). However, since a partially terminated chemical oxide will continue to grow, clusterability of the clean system to the dielectric deposition system may be desired.
An additional benefit of the ozonated clean is that it will not etch the silicon substrate, whereas the SC1 portion of the standard RCA clean has long been known to etch silicon. Two vital concerns with silicon etching are the carrier mobility and channel doping — silicon etching will degrade mobility and modify channel-doping levels. These concerns could be magnified as device manufacturers employ double- or triple-gate configurations or migrate to SOI and strained silicon substrates.
Unfortunately, one of the key mechanisms for particle removal is silicon etching in the SC1 solution to undercut and remove particles. The use of standard batch megasonic systems will help particle removal, but will cause damage to high-aspect-ratio structures. This may be alleviated through the use of single-wafer megasonic systems.
For high-performance applications targeting <1.0nm EOTs, the focus will be on ensuring that there is minimal oxide on the silicon prior to dielectric deposition. HF-last process sequences may need to be adjusted to limit the exposure to post-HF water rinses; current technologies appear to be able to address those needs, although enhanced coordination for clustering wet clean and deposition modules would be useful.
For drying, new solvents need to be developed to provide a more stable surface with fewer contaminates than currently observed with IPA. Nonliquid (i.e., gas-phase) cleaning techniques may prove advantageous, especially in a clustered configuration, but they must provide a damage-free stable surface, which is still a state-of-the-art challenge. Subsequent high-k growth kinetics will also determine the starting surface requirements and thus the applicable cleans technologies, including the chemical termination at the surface and, therefore, the initial interfacial oxide thickness.
In all cases, a major challenge is to ensure the initial pristine silicon-dielectric interface (and dielectric thickness) is retained during subsequent high-k deposition and thermal processing (with appropriate ambient conditions).
More energy needed
D. Martin Knotter, principal scientist, Philips Semiconductors, Cleaning Expertise Center, Nijmegen, The Netherlands
 D. Martin Knotter |
Since the general thought is that killer particle size scales with the technology node, the relative bond strength of killing particles attached to the surface increases. This means that the forces necessary to remove particles from future wafers increase.
Furthermore, laws of chemical physics state that tearing two bodies (i.e., particle and substrate) apart costs energy and a part of this energy is returned by the formation of new interfaces (particle to liquid-gas and substrate to liquid-gas). In a liquid, the return is larger than in a gas, which makes it energetically more favorable to remove particles in a liquid than in a gas. This does not mean the end of possible laser technology that shoots particles from the wafer with a laser beam, but in general, the presence of a liquid helps.
Wet megasonics is currently the method of choice to remove particles. The removal force is probably the shear of moving liquid. Shear forces drop as a function of distance to the surface; the closer to the surface, the lower the force. In other words, the smaller the particle, the lower the available removal force, necessitating higher energy. While increased megasonic power can be a solution, it increases the potential for damaging IC structures.
One of the additional issues is the intrinsic nonuniformity of the megasonic power. To remove particles from a whole wafer, power has to be tuned so high that damage may result. Additional help for wet megasonics is chemical etching, but the requirements of material loss during cleaning become so small that etching is no solution.
Another method to remove particles is based on surface tension. When a particle on a surface moves through a liquid-gas interface, forces on the particle become high and the particle is removed. There are two methods of exposing a surface to many of these interface passes in a short time — using small droplets impinging on the wafer or using multiple, foam-like gas bubbles. The first concept is already a commercial product, but the second is not.