Beyond the 100nm node: Single-wafer RTP
05/01/2003
Overview
Key developments such as improved spike anneal temperature control, enhanced low-temperature processing capability, and a radical-based oxidation process are extending the capabilities of rapid thermal processing for applications such as ultra-shallow junction activation and anneal, silicidation, and shallow trench isolation liner oxide formation to meet projected industry roadmap requirements for sub-100nm device design nodes [1].
As the semiconductor industry approaches sub-100nm device design nodes, it is faced with many thermal processing and integration challenges [1]. These challenges include the following:
- control of self-aligned doping processes and thermal activation budgets to achieve ~15%, 3s Leff control;
- coping and activation processes to achieve shallow source/drain regions having parasitic resistance that is less than ~16–20% of ideal channel resistance (Vdd/Ion);
- formation of self-aligned silicide over shallow source/drain regions; and
- maintaining low device leakage with increased packing density and shrinking STI geometries.
Advances are extending process capability to sub-100nm nodes for ultra-shallow junction (USJ) activation and anneal, silicide contact formation, and thermal oxidation STI formation. Improved spike anneal temperature control results in enhanced within-wafer and wafer-to-wafer process uniformity. Anneal process temperatures have also been extended down to 300°C for nickel silicide formation, as transformation from nickel to nickel silicide occurs in the 300-450°C range for typical nickel film thicknesses. A proprietary rapid thermal processing (RTP) radical-based oxidation process, in situ steam generation (ISSG), can grow thermal oxides for STI liner and sacrificial oxide to improve transistor characteristics and device performance [2, 3].
Enhancing spike anneal productivity
Ultra-shallow junctions are formed using a combination of ion implantation and RTP spike anneal. Low-energy ion implantation of dopants into the wafer is followed by a rapid thermal processing spike anneal to move dopant species to active sites in the silicon lattice and to repair implant damage.
The tight temperature uniformity of RTP spike annealing must be continuously improved as the industry transitions to the 300mm wafer size and to smaller device geometries. Small variations in temperature across the wafer may induce nonuniformity that could decrease product yield on the wafer by increasing within-wafer Vt variation. Vt sensitivity to spike anneal peak temperature increases as the channel length decreases [4].
Thus, as device dimensions shrink, a given thermal variation across the wafer results in an increasingly more pronounced device-to-device Vt variation. Spike anneal temperature control, therefore, is growing in importance as a critical factor in achieving optimal product yield and device performance.
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As the 300mm RTP spike anneal process has matured, chamber enhancements have led to improvements in temperature uniformity across the wafer. Changes include optimization of the process kit, ramp-up and rampdown methodologies, and radiative and conductive heating/cooling.
Within-wafer uniformity has been improved while maintaining spike sharpness, peak ramp-up and rampdown rates, and critical electrical device characteristics. Figure 1 shows the process result for a 500eV, 1E15atoms/cm2 boron implant with an improved 1050°C spike anneal. The demonstrated within-wafer uniformity is <5°C, 3s. This enhanced performance is expected to significantly improve device yield and add considerable value to the device performance on the wafer.
One process improvement — the enhanced Emissometer — increases the sensitivity and robustness of an RTP chamber's in situ emissivity compensation, which is required for precise and repeatable temperature control across varying wafer backside emissivities. The enhanced Emissometer improves the measurement accuracy for all RTP processes, but most significantly for transient processes such as spike anneal, while preserving emissivity independence for the wide emissivity range of 0.3–1.0.
Advanced silicide contacts
The challenge for salicide processing is to produce low sheet resistance contacts to highly doped, shallow source/drain and source/drain extension junctions. RTP processing supports cobalt silicide formation, which requires a first anneal in the 400–550°C range for formation of the intermediate CoSi phase and a second anneal in the 700–800°C range for conversion to the final, low-resistivity CoSi2 phase (after stripping off the unreacted metal).
Multipoint temperature control with a 100Hz sampling rate minimizes added nonuniformity as the wafer ramps through the temperature-sensitive transformation regime. Since cobalt is highly reactive in the presence of oxidizing species, maintaining oxygen concentration below 1ppm is critical to prevent oxidation of the exposed metal surface that competes with silicidation at the metal-silicon interface.
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As the industry approaches sub-100nm nodes, the trend is to replace cobalt silicide with nickel silicide for source/drain metallization. One of the primary advantages of nickel silicide is the reduction in junction silicon consumption (Fig. 2) required to form the silicide as compared to cobalt silicide. Cobalt requires 3.64Å of silicon/Å of metal to form the low resistivity CoSi2 phase, while nickel requires only 1.83Å of silicon/Å of metal to form NiSi. Furthermore, nickel silicide has a lower sheet resistance than cobalt silicide, and formation occurs without agglomeration at a lower temperature [5].
Device manufacturers select their silicide anneal temperature based on process and thermal budget integration requirements, with the typical nickel silicide anneal range being 300–450°C. Temperature control has been extended down to 300°C with system modifications. The challenge for low temperature control is to increase the infrared signal-to-noise ratio to obtain accurate and repeatable IR pyrometer readings. Figure 3 illustrates the result of closed loop control down to 300°C and to within ±1°C of setpoint. The benefits of this optimization extend to all processes, as the more robust low-temperature control results in smoother open-to-closed-loop control transition even for high-temperature processing.
Shallow trench isolation
At sub-100nm device nodes, implementation of STI becomes more challenging, incorporating aspects of trench definition (lithography, etch), liner oxidation, trench fill with deposited oxide, CMP, and another thermal oxidation to grow the sacrificial oxide. The step following the trench etch is liner oxidation, which is important as it can adversely impact transistor performance if not implemented successfully.
 Figure 3. Radiance chamber low-temperature control at 300°C with a blanket nickel wafer showing control to within ±1°C of setpoint using closed-loop control. |
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The liner oxidation step is necessary to round the top and bottom trench corners. Rounding of the sharp, top corner is critical for optimal transistor characteristics — sharp corners at the top of the trench near the active area result in crowded electrical fields and an undesirable kink in the sub-threshold I-V transistor characteristic due to the parasitic corner transistors. Top corner rounding also minimizes shifts in threshold voltage and prevents premature gate dielectric breakdown [6–9].
Rounding of the bottom corner minimizes the formation of stress-induced silicon defects that can induce junction leakage current when propagated in subsequent thermal and implant processes. The sacrificial oxide, following the CMP and pad oxide and pad nitride removal steps, is typically viewed as a noncritical oxide. However, recent studies have shown the impact of sacrificial oxide on minimizing stress-induced defects and consequently on improving device yield [9–11].
Conventional liner oxide growth methods include dry and wet furnace oxidation at lower temperatures of 900–1000°C. These techniques face challenges for modulating the trench profile for sub-100nm device nodes. Low-temperature oxidation does not sufficiently round the top trench corner to minimize the parasitic corner transistors, and it also may show faceting effects, potentially leading to stress-induced defects and leakage sites [7]. Furthermore, since wet furnace oxidation does not grow thermal oxide conformally in the trench, it consumes a greater amount of active area to achieve the same corner rounding as achieved with ISSG oxidation.
Although implementing a pad oxide undercut can enhance top corner rounding, it also consumes silicon in the transistor's active area, compromising device characteristics such as drive current [6]. Similarly, sacrificial oxide is typically grown via wet or dry furnace oxidation.
Due to the higher thermal budget and longer oxidation times associated with furnace processing, there is reoxidation of the STI corners and sidewalls during growth of the sacrificial oxide. This reoxidation results in a volume expansion, causing high stresses at the trench corners and potentially leading to stress-induced defects [9–11].
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High-temperature ISSG can address the limitations of other thermal oxidation methods for growing the STI liner and sacrificial oxide. For example, ISSG rounds both the top and bottom corners of the STI trench in a single step with minimal consumption of active area. The oxidizing radicals promote aggressive oxidation achieving good top and bottom corner rounding with reduced crystallographic-orientation dependence [10]. Its effectiveness in rounding the trench corners and growing a conformal oxide is demonstrated in the transmission electron micrograph (TEM) cross sections of STI structures (Fig. 4). The conditions to grow approximately 120Å of oxide were 33% H2 in O2 at 1150°C at a nominal pressure of 10torr.
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ISSG is also used for STI liner and sacrificial oxidation because it demonstrates significant advantages, including improved overall device yield (see table) for one memory manufacturer [2, 9–11]. The yield improvement using ISSG for sacrificial oxidation is attributed to a lack of trench reoxidation at the top corner and edge due to the reduced thermal budget of single-wafer RTP. There is minimal diffusion of oxygen to the trench corners and sidewalls due to the fast temperature ramp rates in RTP as well as the fast ISSG oxide growth rates, thus minimizing trench reoxidation and subsequently stress-induced silicon defects.
 Figure 5. RTP ISSG (the squares) improves Ion for a given Ioff vs. furnace oxidation (the triangles) for a 0.18µm CMOS device. Data courtesy of STMicroelectronics. |
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In another example, the use of ISSG for STI liner and sacrificial oxide improved Ion/Ioff by approximately 10% for PMOS devices (Fig. 5). Consequently, ISSG is being adopted for production for STI liner oxidation and sacrificial oxidation for sub-100nm devices.
Conclusion
Single-wafer RTP is extendible to sub-100nm nodes. Spike anneal temperature within-wafer uniformity has been improved while maintaining spike sharpness. Enhanced low-temperature control allows robust processing for nickel silicide formation down to 300°C. In situ steam generation for STI liner and sacrificial oxidation rounds the trench top and bottom corners by growing a conformal oxide and minimizes stress-induced defects, ensuring good device performance.
Balasubramanian Ramachandran, Hali Forstner, Emily Chiao, Gary Miner, Brian Haas, Applied Materials Inc., Santa Clara, California
Acknowledgments
The authors acknowledge the collaboration of STMicroelectronics and NEC in the data presentation for this article. The support and contributions of Ben Bierman, Greg Redinbo, Raman Achutharaman, Sundar Ramamurthy, Ravi Jallepally, Gia Pham, Toni Wisco, Stephen Nagy, Sai Tallavarjula, and Faran Nouri of the Transistor Systems Group at Applied Materials are appreciated. Radiance and Emissometer are registered trademarks of Applied Materials Inc.
References
1. 2001 International Technology Roadmap for Semiconductors: Front End Processes, (http://public.itrs.net/Files/2001ITRS/Home.htm).
2. S. Kuppurao, H.S. Joo, G. Miner, "In Situ Steam Generation: A New Rapid Thermal Oxidation Technique," Solid State Technology, 43(7) p. 233, July 2000.
3. T.Y. Luo, et al., "Effect of H2 Content on Reliability of Ultrathin In Situ Steam Generate (ISSG) SiO2," IEEE Electron Device Lett., 21, 430, 2000.
4. A. Al-Bayati, et al., "Advanced CMOS Device Sensitivity to USJ Processes and the Required Accuracy of Doping and Activation," Ion Implantation Technology Conference 2002.
5. S.P. Murarka, Silicides for VLSI Applications, Academic Press, New York, 1983.
6. M. Nandakumar, A. Chatterjee, S. Sridhar, K. Joyner, M. Rodder, I-C. Chen, "Shallow Trench Isolation for Advanced ULSI CMOS Technologies," 1998 IEDM Tech. Digest, p. 133.
7. T. Speranza, et al., "Manufacturing Optimization of Shallow Trench Isolation for Advanced CMOS Logic Technology," presented at 12th Annual IEEE/SEMI Advanced Semiconductor Manufacturing Conference, (ASMC) 2001.
8. C.S. Olsen, F. Nouri, M. Rubin, O. Laparra, G. Scott, "Stress Minimization of Corner Rounding Process during STI," presented at SPIE Conference on Microelectronic Device Technology III, Volume 3881, p. 215, Sept. 1999.
9. P. Ferreira, R-A. Bianchi, F. Guyader, R. Pantel, E. Granger, "Elimination of Stress Induced Silicon Defects in Very High Density SRAM Structures," presented at the 31st European Solid-State Device Research Conference, Sept. 2001.
10. K.C. Chen, et al., "Cycle Time and Process Improvement by Single Wafer Thermal Processing in Production Environment," presented at the 10th Int'l Conf. on Advanced Thermal Processing of Semiconductors RTP 2002, Sept. 2002.
11..T. Luoh, et al., "Stress Release for Shallow Trench Isolation by Single-Wafer, Rapid-Thermal Steam Oxidation," presented at the 10th Int'l Conference on Advanced Thermal Processing of Semiconductors RTP 2002, Sept. 2002.
Balasubramanian Ramachandran received his BS in electrical engineering at the Indian Institute of Technology, Kanpur, India. Ramachandran is currently a process engineer in RTP at Applied Materials.
Hali Forstner received her PhD in chemical engineering from the California Institute of Technology. She is currently a member of the technical staff at Applied Materials.
Emily Chiao received her BS in chemical engineering from Stanford University. Chiao is currently a process engineer supporting Applied Materials RTP Products, 2727 Augustine Drive, Mail Stop 0766, Santa Clara, CA 95054; email her at [email protected].
Gary Miner received his MSEE from Stanford University. He is currently director of RTP applications technology at Applied Materials.
Brian Haas received his PhD from Stanford University. He is currently general manager of the RTP product group at Applied Materials.