Current challenges dictated by today's IC packaging trends
04/01/2003
With all the attention given to wafer processing, IC advances, and microelectronics end products, we tend to lose sight of the fact that IC packaging is also being pushed to a higher level of sophistication. There is an increasing demand for high-level coordination between silicon and package designers much earlier in the new product development sequence. The net result is an unprecedented rate of advanced IC package solutions that make our techno gadgets work.
Today, most package proliferation can be attributed to technical and cost demands placed on the package by device and system engineers. Along with increasingly complex package selection decisions, electronic component manufacturers also face difficult decisions about which functional blocks of a system should be partitioned into an individual package in the first place. System level integration in an IC package (system in a package, SiP) is fast becoming the approach of choice for many high-performance and space-sensitive applications.
Along with these trends comes a more intricate supply chain and a host of technical challenges requiring new levels of cooperation among device, package, and end-system design and manufacturing companies.
Packaging demands
Package proliferation is primarily a response to performance demands being placed on the package by the continuous evolution of semiconductor device and end-product system technology. On the device side, smaller lithography, higher operating frequency, higher power dissipation, and increasing numbers of interconnects to other components all lead to continuously evolving package structures and assembly technology. Thinner, smaller end-products with increasing functionality also create challenges for existing packaging. If cost could be ignored, it is likely that a small number of package structures could adequately support all these device and system level requirements. Given the extreme cost pressure throughout most of the electronics supply chain, however, package solutions that offer just the right level of performance at the lowest cost will continue to be used.
Although the wide adoption of area array packaging has significantly changed the nature of IC packaging, this has not stopped proliferation of traditional leadframe-based technology.
For example, ExposedPad and MicroLeadFrame are technologies where packaging innovation has allowed the extension of more traditional package structures into more demanding applications (Fig 1):
- With ExposedPad, the die attach paddle, which has been fully encapsulated inside packages for 30 years, has been moved downward and exposed on the backside of the package, allowing for double the power handling capability and a significant reduction in package loop inductance when the paddle is used as ground.
- MicroLeadFrame takes this thinking a step further by replacing traditional external leads with lands on the bottom side of the package. This modification allows package size to be reduced by 60% and further reduces lead inductance for high-frequency applications.
 Figure 1. A MicroLeadFrame showing an ExposedPad (the large metal square) and bottom-side lands. |
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Both these technologies have been extremely successful in the market because they provide the right level of performance, at the right price, for many demanding applications.
Area arrays
The proliferation of area array packages built on flexible film and rigid PCB substrates is even more pronounced. Nearly every semiconductor device can benefit from customized design of the package substrate to optimize signal routing and improve thermal and electrical performance. Substrate tooling costs can be two orders of magnitude less than those for stamped leadframes.
Elimination of this cost barrier has resulted in the wide use of customized substrate designs for area array packaging. The need for customized substrate designs increases at higher operating frequencies. Just a few years ago, most package electrical parasitic models were created after the substrate design was completed. In many cases, their use was limited to filling in space in a data sheet. This approach no longer works in many high-speed designs. The package substrate must be designed with full consideration of its impact on the electrical performance of the circuit. In an increasing number of cases, device, package, and system design must be accomplished concurrently to achieve first-pass functional success.
This need for concurrent design will only increase as packages become more application-specific. Semiconductor design houses and integrated device manufacturers will need to deliver optimized package designs to allow their devices to function. The expertise to design these packages will need to be developed internally or delivered through partnerships with packaging providers. As proliferation of package structures and materials continues, more and more resources will be required to ensure that the package does not limit device performance.
Area array packages are also regularly modified to provide optimized thermal performance at the right price point. Consider the range of area array packages and their relative thermal performance (Fig. 2). Package acronyms are defined in the table. Certainly, every engineer can understand the importance of selecting a package with a sufficiently low thermal resistance to match the device power dissipation needs. Since electrical performance also differs among these options, certain applications may demand a more detailed understanding of the attributes of alternative structures. More challenging, however, is selecting the lowest-cost alternative that meets the required performance criteria. This decision requires a detailed understanding of the performance of each package configuration and knowledge of the device power generation, as well as the ability of the system environment to dissipate heat.
Chip scale packages
The introduction of array molding and saw-singulated chip scale packages (CSPs) has further eliminated barriers to package proliferation. In the past, a high-volume package-assembly tooling set for a traditional individually molded and punch-singulated package could cost more than $500,000. Today, an existing saw-singulated package assembly line can be re-tooled for <$50,000.
The elimination of this cost barrier has played a big role in the rapid growth in the number of available package options over the last few years. Consider package thickness proliferation of area-array saw-singulated CSPs (Fig. 3). The incremental tooling cost of each progressively thinner version is small. Within each family, packages from a few millimeters square to more than 20mm2, and a few terminal balls or pads to several hundred, can be manufactured with relatively small additional tooling investment. Rectangular shapes, various terminal pitches, depopulated arrays, and other options can be added as needed to optimize performance at the lowest cost.
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Early coordination
The proliferation of package structures creates profound challenges for semiconductor device and packaging companies. The challenges begin at the design stage. No longer can package design begin after the device design is almost complete. Nearly every device requires custom substrate artwork. Various configurations of assembly tooling must be prepared and managed prior to initial builds. This custom assembly tooling can include not only traditional die attach and wire bond fixtures, but now also custom mold cap, ball attach, saw singulation, and shipping tray tooling.
With the intense time-to-market pressure on most new designs, nobody wants to explain to their boss or customer that their new wafers coming out of fabrication cannot be assembled due to the failure of the packaging group or contractor to prepare tools and materials properly.
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This problem has led us and other large assembly houses to re-engineer the new product introduction process. With hundreds of custom designs being completed quarterly, and customer and factory sites around the world, a web-based project management work flow engine can greatly reduce time-to-market and human workload and ensure that every design is built right the first time.
For example, our customers use a web-based new product introduction tool that captures design requirements. Depending on specific design requirements, anything from a simple substrate layout or a complex co-design including full thermal and electrical modeling and optimization is initiated and tracked through completion. The final package tooling requirements and manufacturing location are compared to a database of available tooling. New tooling requirements for mold tools, ball-attach tools, singulation tool, electrical sockets, etc. are highlighted and the procurement process is initiated and tracked. Substrate artwork and piece part orders such as heat slugs and passive components are also initiated and tracked through the system. As a result, preparation of the complete manufacturing kit can be managed efficiently and quickly to speed customer's products through the assembly process and on to end-users.
 Figure 3. Thickness proliferation of CSP formats. (Acronyms are defined in the table.) |
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Continuing complexity
Package complexity will probably continue to increase. SiP has emerged as a cost-effective and flexible way to achieve integration of complete electrical functional blocks within a package (Fig. 4). High-volume commercial and consumer applications are benefiting from the integration of multiple semiconductor devices with other passive and active components within a conventional IC package. While system on a chip (SOC) will continue to be a focus area for many electronics companies, more applications are taking advantage of package-level integration to deliver complete subsystems to their customers.
SiP allows smaller, more standard silicon designs to be combined to create functional blocks of the final system. High wafer-fabrication mask costs, short product lives, and relatively low-yielding, mixed-technology wafer-fabrication processes make SOC undesirable for some applications. Some SiP applications solve these problems by assembling multiple devices into a single IC package. Logic and memory combinations are prevalent. The logic device can be combined with various memory capacities to customize the packaged product for different applications.
 Figure 4. SiP incorporates multiple semiconductors with other passive and active devices in a small footprint. |
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In RF applications, where passive network design is critical to complete the subsystem design, SiP can move this complexity off the system board and into the package. This approach is becoming common for wireless applications, where standard radio components can be used to deliver wireless connectivity to a variety of end-products without the need to have extensive RF design capability.
Although the ability to screen out bad devices at die level for multichip modules continues to create challenges for the industry, in many cases the yield loss associated with SiP is far better than that achieved when integrating multiple technologies at the wafer-fabrication level.
3-D packages
Three-dimensional packaging is an approach that is gaining wide acceptance for space-constrained SiP applications. Stacking silicon die inside a package allows multiple device types to be integrated into the same space as a single die. The vast majority of mobile phones produced today employ this technology. FLASH and SRAM memory are commonly stacked inside a single CSP.
Going forward, the move to 2.5G and 3G cell-phone functionality will require a higher level of integration. Many companies will integrate the digital base band processor device and potentially other ASICs for functionality, such as MP3 decoding and GPS processing, into stacked configurations with increased capacity memory device.
The challenge bottom-line
Increased package-level integration creates a number of new challenges for the electronic supply chain. Various silicon devices in a single package may not come from the same semiconductor company. The traditional model of semiconductor companies consigning wafers to packaging companies cannot easily manage this new complexity. New levels of cooperation are required between semiconductor companies, packaging companies and end users to develop a supply chain that allows efficient implementation of integrated designs and maintains a fair allocation of inventory and yield risk.
Testability of various components within a packaged system needs to be considered and the appropriate level of capability designed into the system. A great deal of activity is currently ongoing in this area. Although the optimal business model has not yet emerged, key attributes are beginning to be defined. Certainly, the demands of future high-speed and highly integrated end-products make identification of this process an imperative. New levels of cooperation between various companies delivering technology in their area of core competency must be at the center of this new business model. The near future of IC packaging includes the integration of MEMS, optical, and photonic devices into subsystems including semiconductors. A host of technical challenges such as protection of moving machine components, particle control and lens mounting, and fiber alignment will come on top of the package proliferation and integration challenges discussed above. Successfully overcoming these challenges will pave the way for a world of techno-gadgets unimaginable today.
Package proliferation is the direct result of the demands being placed on the traditional IC package by evolution of device and system technology. As applications become more demanding, packaging technology expands to deliver the optimal solution at the lowest cost. The reduction in tooling costs associated with newer packaging technology has eliminated many of the barriers associated with package proliferation in the past. This has created new problems in delivering mass customized package solutions in high volume with short lead times. Increased levels of integration in packaging enable smaller and better-performing end-products but create new challenges for the traditional electronics supply chain.
Scott Jewler, Amkor Technology Inc., Chandler, Arizona
Acknowledgments
ExposedPad and MicroLeadFrame are trademarks of Amkor Technology.
Scott Jewler is senior VP, Assembly Business Unit, Amkor Technology Inc., 1900 S. Price Rd., Chandler, AZ 85248; ph 480/821-5000, [email protected].