200mm vs. 300mm manufacturing
04/01/2003
Solid State Technology recently asked a number of industry professionals to comment on the future of 200mm vs. 300mm manufacturing. Here are several views on the topic.
Through the looking glass of disruptive technology
Steven M. King, Matthew Verlinden, Integral Inc., Boston, MA, Clayton M. Christensen, Harvard University, Cambridge, MA
The pursuit of Moore's Law has been the driving force in the semiconductor industry since the law's formulation in 1965. Chasing the next technology node has delivered enormous value to the market and to the companies that have enabled this progress.
There is evidence, however, that the rewards for manufacturing devices on the latest cutting-edge technology node are decreasing. Will competitive advantage continue to reside in the ability to produce 130nm feature sizes on 300mm wafers?
 Clayton M. Christensen |
Although we do not have conclusive technical and economic data, our research suggests that the basis of competition in the semiconductor industry is changing. It isn't at all clear that 300mm will be the driving force in the future that wafer size transitions have been in the past. To explain our view, we look at the semiconductor industry through the predictive lens of the disruptive technology framework.
In describing why great firms sometimes fail while doing everything right, the term "disruptive technology" was coined by Clayton Christensen [1]. He has shown that the interaction of two trajectories — the pace of performance improvement that innovative firms make available, and the rate of improvement that customers can utilize — triggers fundamental changes in the way companies need to compete. The performance delivered by products can, over time, come to exceed what customers in any given tier of the market can utilize, or most important, are willing to pay for. When this "performance overshoot" occurs, customers cease to value further improvements on that measure. Although they will gladly accept increased performance, they will be more and more unwilling to pay a premium for it. Market forces then compel companies to find new ways to compete. Examples of such alternative dimensions of competitive improvement include convenience of use, product variety and/or ease of customization, and speed to market.
 Steven M. King |
In the semiconductor industry, the signposts indicating performance overshoot are becoming increasingly clear. For example, the speed of general purpose microprocessors, while still not good enough for bleeding-edge customers, is far greater than the demands of most mainstream users. The competitive forces that have already taken hold in less demanding market tiers — speed to market, and the ability to conveniently custom tailor the features and functions of devices to the needs of specific classes of customers — will be the types of innovations that matter in the future. Dell's innovative business model for supplying customized products quickly in the PC industry is analogous to the type of business model that will emerge in the semiconductor industry.
 Matthew Verlinden |
Another example of the shift in the basis of competition in the semiconductor industry is the recent actions of fabless semiconductor companies. Fabless companies have backed away from having designs produced at the newest technology node in favor of less expensive and proven manufacturing processes. They have succeeded with this strategy; the fabless sector of the industry grew 10x faster than the overall in 2002, based on revenues.
The semiconductor equipment industry is also feeling the effects of the phenomenon of performance overshoot and the changing basis of competition. The International Technology Roadmap for Semiconductors (ITRS) suggests that the price delta from 200mm to 300mm tools be 1.3x, not the 2.4x many equipment suppliers were expecting. So the question must be asked: How much does the market really value the performance promised by 300mm tools?
We believe there will deep and unavoidable changes in semiconductor manufacturing. In the past, production facilities were designed to produce high volumes of standard parts; cycle time was not as critical and low yield was compensated for by high-margin products. With the competitive shift to speed to market and customization, fabs need to produce lower volumes and smaller lots with high product mix.
It is safe to assume that as competitive pressures to be faster intensify, someone will figure out how to move away from high-WIP wafer-lot approaches, and produce semiconductor products in a low-WIP, single-wafer, connected flow format.
We posit that movement toward single-wafer processing would likely compromise the economic viability of investments in current 300mm wafer-processing equipment.
When manufacturing plants in other industries have converted to low-inventory process flows, the effective capacity of the plants typically doubles, with minimal additional capital investment. Hence, a fab processing 200mm wafers in a single-wafer flow would be expected, over time, to start twice the number of wafers/month (and nearly 90% the number of the die) as a conventional fab processing 300mm wafers — and to do so at much lower cost and complexity levels.
In other industries, where the conversion to low-WIP, connected flow processes has been achieved, successful managers have employed the simplest, most reliable, and proven equipment possible. They accept less proven equipment technologies only after the process is well controlled. Because the ability to produce the next generation of finest feature sizes is likely to be provided primarily in 300mm equipment, we will likely see 300mm equipment deployed only in the most demanding tiers of the market (where throughput speeds are less important). With the overshooting phenomena described above, it is possible that 300mm equipment will become dominant in other tiers of the market slowly, if at all.
Reference
1. C.M. Christensen, The Innovator's Dilemma: When New Technologies Cause Great Firms to Fail, Boston, Harvard Bus. School Press, 1997.
For more information, contact Matt Verlinden, ph 617/425-8493, e-mail [email protected].
Is there life in 200mm manufacturing?
Daren L. Dance, Austin, Texas
For the last five years or more, 300mm wafers have been the big news for semiconductor manufacturers. But what if you don't have the $1–3 billion that building a 300mm fab may cost? One forecast projects that 469 million in.2 more 200mm silicon will be used in 2006 than were used in 2001 [1]. In fact, 200mm wafers will still account for at least 20% of wafer fabrication in 2013. Yes, there is life remaining in 200mm wafer fabrication.
Conventional wisdom has the semiconductor industry focusing on 300mm wafers as the wave of the future. Prior wafer size transitions have been driven by increased IC area, particularly for memory chips. Larger wafers produce more die for the same number of processing steps, thus increasing productivity. Depending on IC area, a 300mm wafer produces 2.2–2.7¥ more testable die/wafer than a 200mm wafer. Manufacturing large complex circuits, such as memory and microprocessor chips, on 300mm wafers can achieve significant cost/die savings. Is this true for all devices?
Compared to MPU manufacturers, memory manufacturers have larger production volumes and lower profit margins. These should also benefit from 300mm manufacturing. Foundries should also significantly benefit from 300mm wafer fabrication as they aggregate wafer orders from many sources. The combined demand provides foundries with the volume on which the 300mm economies of scale depend. Announced plans for 300mm wafer fabs, excluding pilot lines and R&D, include seven memory, six foundry, and four MPU/DSP/logic facilities, according to Strategic Marketing Associates, October 2002. As expected, memory and foundry fabs lead the interest in 300mm manufacturing.
Many comparisons of 200mm fabrication with 300mm fabrication are based on a theoretical 300mm-manufacturing cost model that was published in 1997, well before significant 300mm-manufacturing experience had been accumulated [2]. The assumptions used in this study have been perpetuated, even when actual performance experiences differ. Table 1 summarizes some critical assumptions from the 1997 study and adjustments made to better reflect current manufacturing experience and economics.
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A Factory Commander cost simulation of 200mm and 300mm using the revised assumptions shows the results summarized in Table 2. Under these conditions, die cost from a 200mm wafer may be 28% lower than the die cost from a 300mm wafer.
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The analysis in Table 2 assumes that both 200mm and 300mm equipment are within a normal five-year, straight-line depreciation time frame. If most of the production equipment is fully depreciated, as is the case with many 200mm fabs, the cost/die difference is even more substantial because equipment depreciation costs account for 38% of the 200mm cost/die. Not only is there still life in 200mm wafer fabrication, in many cases there are cost benefits for continuing its use.
While the analysis in Table 2 shows that 200mm wafer fabrication results in a lower cost/die using the assumptions of Table 1, it should also be clear that there are manufacturing assumptions for which 300mm wafer manufacturing may have a lower die cost. Strategic decisions relating to 200mm or 300mm manufacturing are so important that each decision must be analyzed on a case-by-case basis.
Acknowledgments
Factory Commander is a registered trademark of Wright, Williams & Kelly, Pleasanton, CA.
References
1. Rose Associates/IC Insights Inc., as quoted by D. Vogler, "Evolving Business Strategies Are Key to an Upbeat 300mm Outlook," Solid State Technology, p. 27, October 2002.
2. Sematech Technology Transfer 97123418B-ENG, "Tool Performance Requirements and Cost Sensitivity Analysis for 180nm/300mm Aluminum and Copper Interconnect with I300I Tool Performance Metrics," January 31, 1997.
3. International Technology Roadmap for Semiconductors, 2001 update.
4. The 1997 study assumed that process material costs would remain flat at 200mm rates; however, the consumption of many of the more expensive materials, such as photoresist and CMP, increases with wafer area, so the author has assumed a constant multiplier (2.5¥) rather than a flat rate.
5. S. Merchant, A.D. Chasey, "Impact of AMHS on Design and Construction of 300mm Fabs," Del E. Webb School of Construction, Arizona State University, www.fabtech.org/features/.Del.E.Webb/.Index.shtml.
Daren L. Dance was VP of technology at Wright, Williams & Kelly, Pleasanton, CA, when this was written. He can now be contacted at The Fairview Group, 231 Market Place #208, San Ramon, CA 94583; ph 512/659-8262, [email protected].
A continuing market for upgraded 200mm manufacturing?
Paula Doe, Contributing Editor, Solid State Technology
Sematech's industry economic model — an extensive effort involving some four years of development and beta testing by a group of two to three dozen consortium members and suppliers — suggests a continuing market for upgraded 200mm technology.
There could be a significant market for 130nm and even 90nm 200mm tools as revamping 200mm fabs has a significant cost advantage over new 300mm facilities for some products (see Solid State Technology, March 2003, p. 20, "International Sematech: Upgraded 200mm technology saves money" or see the article on www.solid-state.com).
Acceleration of the technology roadmap, however, means a significantly reduced market for fab equipment suppliers (For more information, read the following short piece: "Acceleration of roadmap could be bad news for wafer fab equipment market.")
Those are two of the more interesting results from the model.
"For an extended period of time, upgrading 200mm-depreciated fabs has reasonable potential in cost per transistor," notes Denis Fandel, Sematech project manager for productivity analysis, manufacturing methods . "There are fairly significant advantages through three to five years, suggesting there's a segment of manufacturers in our industry that will continue to push the technology at 200mm."
But the model indicated bad news for the fab equipment industry with the acceleration of technology. "It showed that if we continue the two-year acceleration, it does unfortunately depress the fab equipment market in terms of how much revenue it will generate," continues Fandel. He thinks the model is stabilized enough now so that it can go to production mode this year and be made more widely available in some form.
The core of the tool is Sematech's cost resource model for the fab, which inputs everything from chemical usage to tool throughput and downtime by process to figure out industry capacity and cost. It also inputs data on product demand, past and future, from Semico Research Corp., and on technology change, from the International Technology Roadmap for Semiconductors (ITRS) roadmap. Advisors at participating companies provide consensus for the input of business factors such as timing of upgrades. A more economically sophisticated dynamic investment module that takes into account how decreasing prices increase demand is also being added. Kenneth Flamm, of the University of Texas, Austin, has demonstrated a prototype that used pricing indexes to generate an expected level of investment in the future, though much work remains to convert the single snapshot into a dynamic tool.
From all this, the model calculates the industry's capacity — by wafer size, technology node, product group, and the like — and how that capacity is accomplished. "The model is intended to be able to dial in numbers around the basic trend to do sensitivity analysis and try different scenarios," states Robert Wright, Sematech's simulation project manager. Over the last few months, he says, the team has demonstrated viability on past data. The next step is to check how well the industry's leading indicators and actual tool purchases match with its calculated needs for forecast production, hopefully providing a warning if tool sales or orders get drastically out of line with forecast chip production.
Other studies using the model showed that next-generation lithography tools should be able to sell for a reasonable price and still cover development costs, and that chipmakers need to get in on the first two or three years of a technology to get the most profit, because by years three, four, and five, the leverage from the technology is lost.
One issue important to equipment suppliers is how the model accounts for market growth. Iddo Hadar, managing director of Applied Materials' corporate strategy office, says that he and AMAT have been heavily involved in development of the Sematech industry model, and continue to support it strongly. The recent study, however, suggesting that the acceleration of the roadmap could mean lower silicon usage and the need for fewer process tools, simplifies things too much by not taking into account future growth in the market. "The bottom line is if technology moves faster, there's more spending on technology," says Hadar, noting that it's illogical to assume demand will stay the same. "For simplicity, they've made a basic assumption that undermines how this industry works."
He notes that while the acceleration of the roadmap in the late 90s to two-year nodes did indeed bring slower growth in silicon consumption, it also brought higher—not lower—equipment sales, as the installed base of equipment got obsolete faster.
But Fandel notes that his demonstration of the funcitionality of the industry model simply shows what happens from changing one parameter, the physical characteristics of the device. He adds that no one has yet developed a model sophisticated enough to properly take into account elasticity of demand to reliably forecast market growth from technological change. The Sematech model is not intended as a forecasting tool, but as an open-ended tool for decision making, useful for seeing what happens if one changes a variable.
Acceleration of roadmap could be bad news for wafer fab equipment market.
The acceleration of the pace of technological change could be surprisingly bad news for semiconductor fab equipment, according to International Sematech's industry economic model. A new technology node every three years from 2003 to 2007 would potentially generate demand for wafer fab equipment in the $40 billion range. But a new node every two years suggests sales would be only a $20 billion/year range, as significantly less silicon area would need to be processed for the same total output of device capability. The analysis deals only with the physical consequences of the roadmap changes, keeping the capital cost/fab the same. Nor does it take into account the potential growth in end electronics systems markets, likely to be sparked by the faster progress of chip technology. Still, that's a sobering amount of growth that would have to be generated by higher tool prices and new demand for faster, smaller chips to make up the difference. -- Paula Doe
