Is total single wafer the fundamental change the industry needs?
03/01/2003
On the worldwide list of 300mm fabs, Trecenti Technologies, Hitachinaka, Japan, may seem like just another advanced foundry. However, it is fundamentally different from other 300mm fabs. Trecenti was conceived as a fully single-wafer 300mm manufacturing operation designed to attack cycle-time reduction and be more cost effective. In addition, its goals include better yields, more flexibility for the supply chain, and more customization for customers.
Dean Strausl, executive director of the Electronics Supply Chain Association (ESCA), Orange County, CA, believes that Trecenti's combination of single-wafer processing and ability to move wafers through its fab at 1.0 day/mask level (its record is a 25 layer device in 5.8 days) represents fundamental changes that bring proprietary advantage back to semiconductor manufacturers.
"In putting the Trecenti fab together, engineers there had to do some creative processing, particularly inventing some chemistry for rapid single-wafer cleaning," says Strausl. "Not all single-wafer processing equipment and processes were commercially available at the time." Trecenti engineers also evaluated simulation results to properly address wafer transport because wasting valuable seconds docking a FOUP is critical when cycle time for a single wafer is a few minutes.
Strausl admits to early skepticism. After many years inside semiconductor manufacturing firms and as a lecturer and consultant, he shared the industry mindset that the 90 to 120 day cycle time in fabs was as irrefutable as the laws of physics.
"A lot of OEMs do not believe it takes this long and often think that business pressure, even intimidation, can cut throughputs," says Strausl. "ESCA tried to educate these companies that the 'laws of physics' dictate long cycle times. At Trecenti, this is still true, but the 'physics' of single-wafer processing are totally different. I have seen firsthand what Trecenti is doing, and the reality is that 100% single-wafer handling has monumental cycle-time change possibilities, as Hitachi executives first concluded back in 1999 when Trecenti began as a joint venture with UMC."
By building its fab as a single-wafer foundry, Trecenti avoided the difficulties of migrating from batch to single-wafer processes where each change necessitates new process characterization. Larger foundries that rely on, or want to extend the life of, batch-processing equipment tend to be stuck in this migration. Strausl says the dramatic improvement in cycle time that Trecenti is showing is a "holy grail" kind of thing for IC manufacturing that shortens development runs and dramatically improves a given company's ability to hit a given market.
"Perhaps more important," says Strausl, "increasingly, fabless semiconductor manufacturers are being forced into using the common processes and design rules offered by large foundries who still rely on a high degree of batch processing. These companies are beginning to wonder where their proprietary position related to cost and performance is going to come from — a position that is beyond their circuit design that could only live for a short period. Ideally, process should optimize design. But when using foundries with batch processing, a fabless manufacturer may end up being only as good as everyone else because everyone has the same thing available to them."
Strausl sees that a foundry with total single-wafer processing changes this scenario. "Using all single-wafer tools means that all wafers in a FOUP could be processed to different profiles at each process step, resulting in a significant change in process step times and conditions. This means that a fabless company can use yield improvement engineering capabilities much like an IDM can, even though its wafers are done at a foundry. This kind of tweaking is virtually impossible at a foundry using batch processing."
While one of the threats in the industry is that foundry capacity is becoming an industry commodity, Strausl thinks that the alternative is single-wafer processing.
Another factor to consider is the effect of outsourcing on the semiconductor manufacturing equipment industry. As more companies outsource, equipment vendors become more distant from the actual users of technology. "The irony is, however, that the equipment vendors are the ones that gave the foundries the technology that rivals IDMs," Strausl says. "So, the next big step for the semiconductor industry, which is already beginning, is disintermediation of the actual foundry process. Savvy companies are forging relations with equipment manufacturers for process IPs and are managing that IP at the fab level."
International Sematech: Upgraded 200mm technology saves money
There could be a significant market for 130nm, and even 90nm, 200mm tools because revamping 200mm fabs will have a significant cost advantage over new 300mm facilities for some products for some time. And acceleration of the technology roadmap could result in a significantly reduced market for fab equipment suppliers.
Those are two of the more interesting results from analyses using International Sematech's industry economic model, presented at its recent Global Economic Symposium in Scottsdale, AZ. The consortium plans to explore ways to make its increasingly sophisticated economic model more widely available to the industry this year.
"For an extended period of time, upgrading 200mm depreciated fabs has reasonable potential in cost per transistor," says Denis Fandel, Sematech project manager for productivity analysis, manufacturing methods. "There are fairly significant advantages through 3–5 years, suggesting there's a segment of manufacturers that will continue to push the technology at 200mm."
Modeling the effect of technology acceleration suggested bad news for the fab equipment industry. "It showed that if we continue the two-year acceleration, it does unfortunately depress the fab equipment market in terms of how much revenue it will generate."
After an extensive effort involving some four years of development and beta testing by a group of two to three dozen consortium members and suppliers, Sematech says its model is ready for prime time, and this year it plans to look for a way to make the sophisticated tool commercially available to the wider industry. "The model is stabilized enough now that we can go to production mode this year," says Fandel. "We want to commercialize it now, though we're not sure yet just how." The most likely option is to find the right partner. "We hope it can be a tool to smooth the cycles," he adds. "We want to find a way to get it out there for wider use to improve the industry."
 Upgraded 200mm fabs appear to have advantages in cost/transistor for 3???5 years. |
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The core of the tool is International Sematech's cost resource model for the fab, which inputs everything from chemical usage to tool throughput and downtime by process to figure out industry capacity and cost. It also inputs data on product demand, past and future, from Semico, and on technology change, from the ITRS roadmap. Advisors at participating companies provide consensus for the input of business factors such as timing of upgrades. Now being added is a more economically sophisticated dynamic investment module that takes into account how decreasing prices increase demand. Kenneth Flamm, U. of Texas, Austin, demonstrated a prototype at the workshop that used pricing indexes to generate an expected level of investment in the future, though much work remains to convert the single snapshot into a dynamic tool. The model calculates the industry's capacity — by wafer size, technology node, product group, and the like — and how that capacity is accomplished.
"The model is intended to be able to dial in numbers around the basic trend to do sensitivity analysis and try different scenarios," notes Robert Wright, Sematech's simulation project manager. Users can see the transparent public model's machinery, and drill down through it to see how many tools or chemicals of various kinds a scenario or forecast would require.
Semi's Global Suppliers Group recently gave the Sematech modeling group the go-ahead to continue their work checking Semi indicators and forecasts with the model. Future workshops on the model are open by invitation to companies that can constructively contribute to the dialogue.
Motorola researchers hone AFM for nanotubes
Using atomic force microscopy (AFM), Arizona-based researchers made a significant advance in the ability to electrically test single or small bundles of electronic molecules for nanotechnology circuitry. This is the work of Motorola Labs' Adam Rawlett, Theresa Hopson, Larry Nagahara, and Raymond Tsui, in collaboration with Ganesh Ramachandran and Prof. Stuart Lindsay at the Arizona State University Dept. of Physics and Astronomy.
The Motorola Labs-ASU approach custom synthesizes a 2nm long molecule that selectively forms a chemical bond to a gold substrate at one end while the other end is a 2nm diameter gold nanoparticle — the conducting tip of an AFM. The AFM tip is used to image and make top electrical contact to molecules of interest. Reportedly, by taking particular care to ensure the AFM tip is in contact with a capping nanoparticle, the current flow in a small bundle of one to five molecules can be measured as a function of the applied bias at room temperature.
Previous work with single organic molecules doing electronic functions has involved test structures containing a thousand or more molecules in parallel. Thus, it has not been possible to know whether the data indicated the true electronic properties of a single molecule or some collective intermolecular characteristics. This inability to screen a single molecule rapidly and easily in a defined and reliable manner has been viewed as one major obstacle in molecular electronics development.
Also, until now most reported measurements have involved molecular metal contact interfaces that are different at the two ends of each molecule. The deposition of evaporated metal to form the top contact does not result in a chemical bond to the molecule, such as that typically found in the bottom contact. This could introduce asymmetries in the molecule's physical and electronic characteristics. There have been experiments on direct and symmetrical measurements of a simple single molecule via a mechanical break junction, but such a measurement is difficult to execute and characterize.
With the new method, the current-voltage curve of a test molecule exhibits nonlinearity in the form of negative differential resistance (NDR), while that of a control molecule does not. The result indicated that the NDR previously observed in bulk measurements of similar molecules exists down to the single or few-molecules level, and hints at the ultimate scaling limit that can be achieved with molecule-based electronics.
Motorola Labs is collaborating with other universities in a research project on molecular electronics that is funded by US DARPA.