Finally! Implementation of low-k (<3) intermetal dielectrics
03/01/2003
In 1993, two-thirds of the leading experts in IC intermetal dielectrics (IMD) expected that IMDs with k<3 would be used at the 0.35µm technology node, and one-third projected their first use at 0.25µm. In reality, of course, we've seen the extension of SiO2 (k ≈4.2) and fluorinated SiO2 (FSG, k ≈3.6) through the 0.13µm node.
The reasons that low-k dielectrics have been so slow (and expensive) to implement have more to do with deficiencies in the materials themselves than with any lack of motivation to use them. If the low-k materials and processes had been "good enough" in, say, 1995, they probably would have been implemented. It is well known now that low-k materials invariably exhibit greatly reduced mechanical properties and poor resistance to oxidation and thermal degradation when compared to SiO2.
The long, arduous and expensive process of implementing low-k IMDs at technology-leading chipmakers has included the following general elements: a) selection from among many low-k materials to a few highly promising candidates; b) parallel process integration efforts and final choice of the low-k IMD material, with a major focus on reliability; c) development of manufacturing processes; and finally d) yield enhancement for the chosen material/process. In some cases, this process has taken more than 10 years. A back-of-the-envelope calculation suggests that the total expenditures to date by all parties to implement IMDs with k<3, which began around 1998, could be more than $250 million.
90nm low-k implementation
Low-k dielectrics are either deposited from formulated solutions using the spin-on process, or from chemical vapor deposition (CVD), typically in a tool provided by a major OEM. The focus on CVD-deposited low-k began in earnest a few years later than many of the spin-on low-k efforts, but the CVD approaches have clearly caught up. For the past year or so, many chipmakers have been finalizing decisions on low-k technology for the 130nm and 90nm technology nodes. More often than not, FSG was chosen for the 130nm node, and represented an extension from 180nm. The majority of technology leaders in the chip industry are implementing IMD with k<3 at the 90nm node.
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The competition among low-k technologies at 130nm and 90nm has been lively, to say the least. The spin-on deposition technology (SOD) has been represented by an organic polymer, characterized by high thermal stability, which, in turn, is attributable to an aromatic polymer structure. The competition is CVD low-k, which is based on the formation of an organically modified SiO2 (also referred to as SiOC, carbon doped oxide [CDO], and OSG [organosilicate]). While the SOD technology is championed by a major chemical company, the CVD technology is represented by several major OEM suppliers of semiconductor fabrication equipment.
Even as the fluorinated silica glass (FSG) was being implemented for production at 180nm, there were important signs indicating the eventual "winner" in the k<3 battle. On the SOD side, there were very few independent claims of success with process integration. The projected widespread implementation for SOD at 130nm was seemingly based on licensing scenarios, relying on the process integration success of the initial SOD user.
In addition, essentially all of the SOD candidates except one had been eliminated from consideration. In contrast, several chip manufacturers announced success in process integration with various CVD low-k materials, indicating that the CVD low-k process was more general. Moreover, it became apparent that the properties of CVD low-k films were more suitable to the IMD application when compared to SOD organic polymers.
Further indications of the success of CVD low-k technology at the 90nm (and 65nm) node were provided in papers presented at the December IEEE International Electron Devices Meeting (IEDM). In the past, many industry technology leaders have utilized the IEDM as a forum to provide technical descriptions of their most advanced chips targeted for manufacturing. Many details of the materials and processes used by leading IDMs and foundries for their pending 90nm and even 65nm processes were revealed.
Taken together, compelling evidence for the success of CVD low-k was provided at the meeting. Examples include: 1) Intel's description of the CVD low-k film used in five of the seven layers of interconnect in its 90nm logic technology; 2) the joint development by Toshiba and Sony of 90nm (CMOS4) and 65nm (CMOS5) system-on-a-chip (SoC) technologies, wherein both utilize CVD low-k for most interconnect layers; 3) TSMC's 90nm CMOS technology for SoC using nine layers of CVD low-k IMD; and 4) yet another 90nm CMOS technology for SoC from Samsung, also using nine layers of CVD low-k IMD.
The CVD low-k technology referred to herein is the first generation. Although these low-k films are formed from different OSG precursor chemicals and are deposited under distinct conditions in different OEM's tool sets, the final films are fairly similar; in particular, they all have similar k values, ranging from ~2.7–2.9. These films will largely replace FSG and will be the predominant low-k films used at 90nm.
65nm low-k implementation
The history of the semiconductor industry suggests that when a new material is implemented into production, there is a great deal of momentum driving the continued use of that material for at least one more technology node. It follows that the nominally k≈2.8 CVD low-k IMDs can be expected to be used at the 65nm technology node.
There is a major drive to implement still lower k IMDs, often referred to as ultralow-k (ULK) IMDs, as evidenced by the various conferences and symposia with sessions dedicated to this topic. It is the consensus among many experts, however, that these second-generation low-k materials, which are typically porous and have k values ranging from 2.5–2.2, will probably not be used in manufacturing at the 65nm technology node.
The table includes recent projections for onset of full production at 90nm, and estimates for 65nm production for a number of leading chip manufacturers [1].
The delay in implementing ULK IMDs is attributable to many factors, including a) the economics (yield-based) drive to use the first-generation, k≈2.8 materials at least twice; b) the poor mechanical properties of ULK IMDs; c) several process integration challenges associated with the weak and porous nature of the materials; and d) the relatively short time window associated with qualification of ULK IMDs compared to the estimated onsets of production at 65nm.
Some would argue that in order for ULK IMDs to be used at the 65nm technology node, they would have to be fully qualified within the current calendar year — a prospect not considered likely. Therefore, ULK IMDs will probably not be used in significant volume production until the 45nm technology node. Since production at 45nm is not likely until 2007 or later, this scenario has significant implications for the many research groups in industry and academia that are focused on these k≤2.5 materials and the tooling used to deposit and process them.
Capacitance in the interconnect rises sharply with decreasing intermetal spacings below the sub-0.25µm regime. How then, one might ask, can first-generation low-k materials be used to maintain performance improvements as dimensions shrink from 90nm to 65nm?
For part of the answer, we can look to the Intel 90nm technology referred to previously. In this process, Intel maintains a very small difference between the k value of the bulk dielectric (2.9) and the effective k value of the dielectric system (including dielectric etch and stop layers, the effective k is ~3.0). By utilizing a single etch stop, and ensuring that it is as thin as possible and has the lowest possible k value, Intel is able to fully utilize the k associated with the bulk dielectric. These strategies will probably be used in the industry more generally to extend the use of k~2.8 CVD low-k films to the 65nm technology node.
Additional strategies can be used to minimize capacitance in the 65nm circuits while remaining with the "conservative choice" of a first generation, k≈2.8 low-k film. These include a) additional layers of interconnect, b) improved design to minimize the length of leads, and c) improved package and board technology to enhance overall system performance. Ours is an evolutionary industry, and at this stage, ULK porous dielectrics still look pretty revolutionary.
Reference
1. For the 90nm full production data: Lehman Brothers Global Equity Research Report, "Semiconductor Equipment Capital Budget Survey," Oct. 9, 2002. The 65nm estimates are the author's own extrapolations based on considerations of both historical trends and the ITRS Roadmap projections.
Neil Hendricks is chief technologist for ATMI Inc. He may be contacted at [email protected].