Stresses and Opportunity Behind Today's Advanced-IC Package Proliferation
03/01/2003
After reading through a recent barrage of new package-design announcements, I queried a few experts about package proliferation and the kinds of engineering and process capability challenges, perhaps stresses, that this proliferation is putting on the semiconductor industry.
 Marcos Karnezos |
Package proliferation is a reality. Marcos Karnezos, CTO of ChipPAC Inc., tells me not to expect anything different; the industry is on a track that will exceed the current population of >900 varieties. "Furthermore, a package, among other things, is a space transformer, and real estate in today's small electronic products is at a premium, so packages will continue shrinking in size," he says.
 Scott Jewler |
Scott Jewler, senior VP of Amkor Technology's Assembly Business Unit, says, "There is definitely a connection between package proliferation and IC and end product technology evolution. As ICs get smaller, faster, and more powerful, and end systems get smaller and more highly functional, packaging technology has to expand to bridge the gap."
Karnezos notes that thickness is a major differentiator in packaging, and small packages will continue getting thinner below today's common 0.8mm profile, down to 0.35mm with ball pitches migrating from 0.5mm to 0.4–0.3mm, following advances in substrate and board technologies (see figure).
At the other end of the package size spectrum, proliferation with BGAs is being driven by system-in-a-package (SiP) with stacked die (e.g., multi-chip BGAs that have ~1000 wires). Lee Levine, senior MTS at Kulicke & Soffa, says that while there are "stresses" in IC assembly processing, "Package design and cost demands override all other requirements."
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Venerable wire bonding is still at the heart of advanced packaging process trends. Shown is a wire bonding production line at ST Assembly Test Services Inc. (STATS) in Singapore.
Furthermore, narrow market windows combined with design complexity and costs "dictates that each new package works the first try and in the shortest time," Karnezos says.
Design demands cause...
 Mark DiOrio |
Mark DiOrio, president and CEO of MTBSolutions Inc., says, "Packaging houses can no longer just make a mechanical migration toward high pin counts, working with a customer's packaging engineer. They must also become involved in electrical design aspects, engaging back to a customer's device designers, so the signal flow is unabated from silicon through the package." For example, with RF applications, these engineers must work together to achieve ultimate component performance through electrical simulations that define the signal characteristics (e.g., time delay, signal loss, signal reflection, etc.) of a package. These values allow a device designer to understand how silicon will perform when coupled to the package and to determine the ultimate performance level of the finished device.
"Most packaging engineers are not trained to enter this realm of signal performance, and if they have the 'tools' they may not be proficient with them," says DiOrio. Thus, there is a severe shortage of the right kind of engineering manpower. "This also works back to sales, because a sale can be quickly lost if the sales team at a packaging house does not have the ability to technically deal with the demands of continuously emerging customers," he says.
To further complicate the situation, Ted Tessier, senior MTS at ST Assembly Test Services, notes that with the current downturn, some IDMs have de-emphasized internal packaging development activities and substantially trimmed associated staff.
"It's increasingly difficult for packaging houses to obtain accurate forecasts of what technologies are required by a given customer and the associated timing for their deployment. In the absence of precise information, packaging subcontractors are forced to define broader, generic development roadmaps, resulting in less focused development efforts at a time when there is less funding available to get the job done."
 Craig Mitchell |
Craig Mitchell, VP of marketing at Tessera Technologies, adds, "Contract assemblers and package houses are looking outside for the engineering bandwidth and process capability needed to keep up with new OEM requirements." Scott Jewler adds that "there is a need for comprehensive applications engineering. It is becoming more difficult to configure the right combination of technology that meets the application requirements at the lowest cost."
What about convergence?
 Ted Tessier |
Historically, the IC industry has used standardization to converge to fewer package types, but this trend may not be relief. Levine says, "The trends continue toward smaller, lighter, faster devices, at an attractive cost. Convergence of package form factors and standards only occurs after initial designs or package types are in mass production. Then, standardization and yield improvement serve to drive down costs. New processes are designed and developed to meet demands of new experimental designs. As these emerging processes find markets, they converge, and new key product families, with form factors consistent with industry standards, come into existence."
When stamped leadframes were the common packaging core, standardization was a stronger driver. Now that etched BGA is the common denominator, changes can be made more easily, which equates to greater proliferation and less standardization, Levine says.
Processing stresses
On the assembly process side, the proliferation of SiPs has been the main driver assembly process technology. Tessier notes, "Over the past few years, stacked die packaging applications have almost single-handedly driven the need for otherwise unanticipated and costly process technology developments. The emergence of 3D packaging technologies and the industry's preoccupation with providing it to the wireless market have resulted in delays in the deployment of process improvements needed for other applications."
 Inside this 1.4mm-thick CSP there are four 0.100mm-thick wire-bonded stacked-die. (Source: ChipPAC Inc.) |
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Karnezos says, "Though the number of die in a package is increasing, package thickness is continuously decreasing in 0.2mm steps. This has created need for a bigger 'technology toolbox,' including wafer thinning to 50µm, thin-die stacking up to six die, die-to-die and reverse wire bonding without special pad design, bonding on overhanging thin die up to 2mm, electrical shielding of RF from digital die in the same package, fine-pitch flip chip on low cost laminate substrates, flip chip attach on the bottom side of a BGA-CSP substrate, and failure analysis capability for stacked die configurations that do not allow access to either side of the die." Levine adds, "Ultrafine <50µm pitch wire bonding, multilevel stacked die with mixed flip chip and wire bonding, and wafer-level packaging are examples of new package processes that enable increased integration, but also demand greater assembly capability, tighter tolerances, better manufacturing control, and improved processes to achieve high yields required for high-volume production."
Some of the current 'stresses' in assembly result from wire diameters <25µm in ultrafine-pitch wire bonding. Levine says, "Most factories handle 25µm bonding wire in normal production, but as wire diameter decreases below this norm, fine-pitch wire bonding becomes even more difficult. The learning curve in going from 25–18µm wire diameter at 40µm pitch is significant; the 18µm wire has only 49% of the strength and 24% of the stiffness of 25µm wire. The result is that factories are dealing with the inherent handling, looping, bonding, molding and testing challenges of this change."
If you add the demands of 300mm and copper low-k interconnect, there is the need for multistep thin-wafer sawing, wire bonding on new interconnect schemes, etc., Karnezos says.
While not directly package proliferation-related, all these demands are overlaid with "green" ones for lead-free processing, putting more restrictions on materials. Karnezos says, "The 260°C reflow temperature of lead-free SnAgCu solder balls requires new die attach and molding materials; halogen-free processing requires new substrate resins and solder masks." A bright spot is that lead-free solder balls seem to have a higher board-level reliability than standard eutectic SnPb.
What's the message?
So, what is the message behind package proliferation? Opportunity!
DiOrio is quick to note, "For those meeting this challenge, they no longer need to solicit orders based on price, but can add value to device performance."
"The size and diversity of the electronics market is so vast that many applications can command packaging technology optimized for a specific price-performance ratio," Mitchell says. "Companies that can ensure broad availability of low-cost, flexible packaging technologies that simultaneously solve the integration and infrastructure challenges will emerge in an extremely strong position."
Mitchell says the need can be met by solving technology and business problems. For example, package platforms must accommodate near-term application-specific requirements, but remain flexible and scalable to support future applications. The ability to integrate die from multiple, even competing, manufacturers has to be addressed from the design stage of new package development. System designers at OEMs, IDMs, contract assembly, and packaging houses must collaborate to determine which functions should or should not be integrated, based upon yield, cost and performance considerations. The industry must address supply-chain fragmentation resulting from the increased trend toward outsourcing to reduce costs.
Mitchell adds, "If there's a silver lining to the economic downturn, it's that the industry is highly incentivized to overcome these challenges to achieve cost and time-to-market goals."
Pieter "Pete" Burggraaf, Senior Technical Editor