A Viable Solution: In Situ Processing for Etch
03/01/2003
Overview
 |
In situ etch processing, where multiple operations are performed in a single chamber without interruption, was previously dismissed by some as impractical. Now, with technologies in place that facilitate implementation and a rare opportunity to re-optimize capital equipment utilization — the transition to 300mm wafers — in situ processing is becoming a viable solution. Progress is being driven by device design complexity, requiring a growing number of process steps and multilayer stacks.
At the 130nm technology node, the introduction of 193nm resists has significantly increased etching challenges due to poor resist selectivity, a problem compounded by much thinner resist layers required to overcome depth of focus limitations. IC manufacturers have thus been motivated to integrate hard masks into the process flow.
Hard masks relax resist requirements to define only the antireflective coating (ARC) layer and hard mask, instead of the entire stack, compensating for reduced resist selectivity. These masks, typically PECVD SiO2, SiON, or Si3N4, minimize aspect-ratio-dependent etching (Fig. 1), which, in turn, eases etch requirements to facilitate using in situ processes. However, their use increases process complexity and requires correspondingly enhanced control.
Increasingly stringent demands for CD control accompany each technology generation. At the 90nm node, gate etch CD variations are targeted at <5nm, 3s for all sources: within-wafer, wafer-to-wafer (WTW), lot-to-lot (LTL), and machine-to-machine (MTM). Assuming variations are random, and only 1nm can be tolerated for each, within-wafer variation must be kept below 4.7nm, 3s. To meet these CD requirements, etch systems must confine the wafer in a rigidly controlled environment. A side benefit of maintaining operating conditions for in situ processing is economic; both silicon and dielectric etching have shown improved mean time between cleans (MTBC). For more on economics, visit the SST web site, www.solid-state.com, pull up this article, and read the short piece titled "Economic impact."
In situ dielectric and silicon etching
To enable in situ processing, memory effects that result in process drift must be minimized, and independent control for optimizing the process for each layer in the stack is needed. For silicon etching tools, typically inductively coupled low-pressure systems, chamber materials are selected to allow the use of different chemistries with minimal memory effects. Automated in situ chamber cleaning strategies are employed to limit drift. Surprisingly, the technologies needed for in situ processing and chamber cleans have been available for the past 20 years. They have not been employed until recently due to productivity concerns. Now, new process stipulations justify their use.
null
Ten years ago, gate stacks could tolerate the process drift that chamber cleaning would essentially eliminate. Now, with growing intolerance to CD variation, the environment the wafer sees must be constant at the start of each run. The importance of chamber cleans after each wafer for in situ processing cannot be overstated, as is evident with extended MTBCs, reported as high as 10¥ [1–3]. The reduction in throughput from in situ processing is more than compensated for by eliminating the time required for wafer transport between process chambers and between process systems, e.g., by eliminating ex situ strips and cleans.
The low-pressure conditions, combined with inductively coupled power under which silicon etch systems operate, make plasma cleaning relatively straightforward, with the plasma diffusing to the chamber wall surfaces. For capacitively coupled dielectric etch systems, cleaning large-volume chambers requires considerable power to reach the chamber walls, often leading to sputtering and erosion of the electrode materials. Therefore, cleaning is likely to create more problems than it eliminates, unless the chamber volume is reduced. By confining the plasma within the vacuum chamber, the dielectric etch system can "behave" like a small chamber. Chamber cleaning is therefore limited to the reduced chamber volume, requiring less cleaning power and eliminating erosion and sputtering concerns. The smaller volume also reduces residence time and corresponding memory effects.
To enable optimal etching of each layer in the stack, the process window must be broadened. For example, chemically dominant, low-ion-energy conditions work well for trimming of resists and organic ARC layers. However, for subsequent etching of dielectric masks, polymer-forming gases with increased ion bombardment are required. Therefore, independent control of key parameters is critical. Solutions include altering gas flows and adjusting temperature profiles quickly and directly to influence CDs and etch rates to meet these challenges.
Hard mask gate stacks
Hard masks alleviate the problem of poor resist selectivity, which often makes them preferred over processing multilayer gate stacks in logic and memory devices. The stack typically consists of five layers. Beneath the resist, a thin ARC made from either organic or inorganic materials is used to minimize standing-wave distortion of the printed lines. The hard mask, gate, and gate dielectric are positioned below the ARC. The gate typically comprises dual-doped polysilicon to optimize threshold voltages and facilitate scaling of p-MOS and n-MOS device characteristics [4]. W/WN/poly-Si is now being used to lower gate line resistivity, particularly for embedded DRAM applications [5]. Gate dielectric integrity must be preserved to ensure high yields.
Currently, ex situ processing is the most common means for etching complex stacks. The gate etch process occurs in two chambers; in the first chamber, the ARC and hard mask are opened, preceded by a resist trim in the case of logic applications. The wafer is then removed for a wet clean, and a hard mask gate etch is performed in a second chamber. Some fabs use the gate stack chamber for both trimming the resist and opening the hard mask, where the wafer is removed for resist stripping and wet solvent cleaning before being returned to the same chamber for the gate etch. Operating in such a manner requires significant buffering of wafers between different etch, strip, and cleaning systems.
In situ processing combines a series of etch steps into one wafer pass with a single recipe under continuous vacuum. The wafer remains in a single chamber from resist trimming to gate etch, eliminating complicated factory logistics and improving factory output. Similar to ex situ process chemistries, in situ uses HBr/O2. or other viable chemistries for resist trimming, O2 for resist removal, CF4/CH2F2/O2 for hard mask opens, and HBr/He/O2 for polysilicon etch. To preserve gate dielectric integrity, the in situ recipe may include hard mask open followed by in situ resist removal. A plasma clean between wafers helps to minimize WTW, LTL, and MTM CD variation.
null
 Figure 3. Typical STI stack illustrates the mechanism for a) top corner rounding and b) actual trenches with top corner rounding. |
null
When doping is not annealed, notching often occurs beneath the mask as a result of inadequate sidewall passivation and enhanced etching of the n+-doped silicon [6–8]. However, by leaving the resist intact after the hard mask open, an option only available with in situ processing, there is a greater opportunity to passivate the heavily implanted region of the gate electrode through redeposition of etched resist by-products (Fig. 2). The same effect is more commonly achieved by using fluorocarbon plasmas to etch through the implanted region, while simultaneously passivating the sidewalls. Conversely, if the gate stack doping is annealed, a passivating plasma is still required to equalize the etch rates of differently doped regions.
With or without annealing, it is important to leave the resist in place after the hard mask open to control hard mask exposure (and erosion) to fluorocarbon etchants, though leaving the resist intact through over-etch can threaten the integrity of the gate dielectric [9]. The problem arises when the gate dielectric is exposed to carbon, a by-product of resist erosion that occurs during subsequent etching steps. One way to keep the resist intact while protecting the gate dielectric is with a pre-endpoint scheme using in situ, real-time interferometry. This method carefully monitors the gate etch to stop before exposing the gate dielectric, then switches to a more selective finishing etch. Residual carbon in the system becomes a nonissue.
Due to questions of whether to strip the resist, and, if so, when and how to passivate implanted regions in hard mask, dual-doped silicon gate etching recipes remain an active area of research.
Shallow trench isolation
Until recently, most fabs etched the trench for shallow trench isolation (STI) using ex situ processing. After the mask and pad oxide are opened, the wafer is removed for resist removal and solvent cleaning before proceeding with the hard mask trench etch. The in situ approach opens the hard mask and pad oxide and etches the trench in the same chamber.
Critical to device performance is top corner rounding, needed to prevent thinning of the gate dielectric at the sharp boundary between the isolation trench and silicon substrate [10]. In the absence of rounding, devices are prone to the "double-hump" effect resulting from parasitic transistor action, where the gate electrode crosses the trench corner with the thinned dielectric. The thin dielectric on the corner can also lead to yield-limiting leakage and reliability problems from dielectric breakdown at lower field strengths.
Rounding the top corner helps prevent dielectric thinning and can be accomplished using a variety of thermal processes, but these approaches compromise the processing thermal budget and add cost by introducing additional steps. In situ processing can achieve top corner rounding without thermal issues by using a highly passivating chemistry during the pad oxide etch and at the beginning of the trench etch.
Deposition accumulates on the sidewall of the resist and hard mask (Fig. 3), thereby extending the mask width to form the corner in the etched trench. Once the corner is formed, the chemistry can be changed to minimize deposition on the mask. While this process can be achieved ex situ, it is a more difficult process; this is because the sidewall deposits are stripped along with the resist, and the hard mask alone has a sidewall aspect ratio that is so small that creating a rounded top corner is problematic.
null
Depending on resist selectivity and trench depth, little or no resist may remain once the bottom of the trench is formed due to extensive erosion during hard mask exposure to the plasma. Mask faceting can also result, distorting the desired trench profile. This phenomenon is considerably more severe with the advent of less etch-resistant 193nm resists, requiring resist removal prior to completing the trench. Stripping the resist without compromising the trench profile can be accomplished by a judicious change in process recipe after resist strip.
Critical frontend dielectric etch
Contacts with high aspect ratios ranging from 10:1 to 20:1 pose the most difficult frontend challenge for dielectric etch. Processing high-aspect-ratio contacts (HARC) and self-aligned contacts (SAC) with requisite vertical profiles and striation-free sidewalls requires a tight reign over highly polymerizing chemistries to balance the trade-off between resist integrity and dielectric profiles. Polymer is added to the chemistry to protect the resist. If not enough polymer is added, severe erosion can occur. If irregular, this erosion can result in roughness and striations. If excessive polymer is added, nonuniform deposition due to concurrent etching and deposition processes can again create roughness and striations. Dielectric etch tools also employ in situ chamber-cleaning strategies to prevent chamber wall contamination and memory effects; this approach is critical to increasing MTBCs and maintaining high productivity.
 Figure 5. A 0.20µm self-aligned contact structure with >20:1 corner nitride selectivity. |
null
At the beginning of 2002, a fully integrated, in situ, HARC etch process went into production. Replacing three separate chambers, a HARC etch, etch stop layer removal, and resist strip were performed in a single chamber. Aspect ratios of 15:1 (0.20µm wide and 3.0µm deep) and vertical etch profiles with striation-free sidewalls were demonstrated (Fig. 4).
The SAC in situ etch process is similar to the HARC, combining SAC etch, resist strip, and etch stop layer removal in one chamber, replacing three. In a customer evaluation, a 0.20µm-wide SAC structure with >20:1 corner nitride selectivity was demonstrated, achieving high etch rates (Fig 5).
Dual damascene etch
Copper dual damascene (DD) clearly represents the biggest challenge in backend dielectric etch processing. The number of dielectric etch steps has increased by a factor >4¥, impacting processing times and cost. Formerly acceptable variation within a process window is now restricted by the need to closely integrate each step with those preceding and following.
What is essentially an overlapping process places greater demands on process repeatability. Though the aspect ratio for DD trenches and vias at <6:1 is considerably lower than for HARC, the applications share the need for vertical profiles and striation-free sidewalls. The introduction of low-k materials adds another dimension of difficulty to the process, since exposure to air can alter the k values. In essence, copper DD processing comprises the most demanding set of processing challenges: large number of steps, material considerations, and particular requirements needed to address profiles and sidewalls.
In situ DD etch processes confine multiple steps to a single chamber, replacing dedicated dielectric etchers for mask and barrier opens and special-purpose tools for photoresist removal. In situ DD processing has been implemented in production using via-first and dual hard mask integration schemes, and provides greater flexibility in process control and the ability to change processes rapidly as etching proceeds through each layer. The integrity of oxygen-sensitive dielectric materials is maintained because the multiple-step process is kept under vacuum. This isolation also eases resist removal, which depends strongly on post-etch exposure of the resist to air.
Economic impact
 |
Device performance is only part of the equation. Studies at Lam have indicated in situ processing has economic advantages, beginning with the total number of process tools needed. Work-flow models have shown decreases in the number of tools required for a given number of wafer starts when in situ processing is used. For example, with a 6-metal-level DD process, 5000 wafer starts/week (wspw) and 75% utilization, the number of etch systems can be reduced by as much as 60% with the implementation of a 4-chamber in situ system (Fig. 1). At the same time, tool redundancy is increased, providing more parallel paths for work-flow, effectively decreasing work-in-process (WIP) and increasing the tolerance of total fab output-to-tool unavailability. The overall effect is better productivity and much lower cycle time. A cost model for etch steps was also applied to a gate stack scheme using an in situ versus ex situ approach (Fig. 2). Normalized CoO was reduced approximately 25% by combining multiple steps into a single in situ sequence to improve capital efficiency.
 |
Variable costs are also affected as the number of process steps increases and recipes become more complex. When the resulting mix of tools used to fully integrate the flow is minimized by in situ processing, the corresponding variable costs of consumables and process materials can also be lowered. Confining processes to a single chamber can be beneficial to minimize defects acquired during wafer handling. The model demonstrates that an order of magnitude increase in defects/wafer pass will result in an order of magnitude loss in dollars, regardless of the cost/chip. Less wafer handling reduces defects, scrap, and cycle time.
Conclusion
In situ processing, enabled by advanced control technology and broader processing windows, has shown clear advantages over ex situ in improving process control and performance. These results indicate that in situ processing may effectively offer a means of lowering risk in this economic climate where wide swings in market demand prevail. Studies have also shown that a reduction in cycle times increases competitiveness by reducing the time to market.
Acknowledgments
We are grateful to Anthony Chen, Vahid Vahedi, Chris Lee, Wendy Nguyen, Alan Miller, Tom Kamp, and Jeffrey Tzong for their contributions to this article.
References
1. B. Richardson, MICRO, pp. 39–43, April 2000.
2. S.J. Ullal et al., J. Vac. Sci. Technol. A, 20, 4, 1195–1201, 2002.
3. S.J. Ullal et al., J. Vac. Sci. Technol. A, 20, 2, 499–506, 2002.
4. C.Y. Wong et al., Proc. IEDM, p. 238, 1988.
5. S. Somekh, Future Fab International, 11, pp. 45–53, 2001.
6. C.G. Van de Walle, F.R. McFeely, S.T. Pantelides,Phys. Rev. Lett., 61, 1867, 1988.
7. E.A. Ogryzlo, D.L. Flamm, D.E. Ibbotson, J.A. Mucha, J. Appl. Phys., 64, 6510, 1988.
8. E.A. Ogryzlo, D.E. Ibbotson, D.L. Flamm, J.A. Mucha, J. Appl. Phys., 67, 3115, 1990.
9. F.H. Bell, O. Joubert, J. Vac. Sci. Technol. B, 14, 3473, 1996.
10 .M. Nandakumar et al., Proc. IEDM, p. 133, 1998.
Richard A. Gottscho received his BS and PhD in physical chemistry from Pennsylvania State University and MIT, respectively. He is VP of conductor etch and resist strip products at Lam Research Corp., 4650 Cushing Parkway, M/S CA3, Fremont, CA 94538; ph 510/572-8555, fax 510/249-4798, e-mail [email protected].
Judy K. LaCara received her BS degree in chemistry from the University of California, Berkeley. She is senior product marketing manager for silicon etch at Lam Research.
James V. Tietz received his BS in chemistry and computer science from the University of Michigan, and his PhD in theoretical chemical physics from the University of Kansas. Tietz is managing director of the Dielectric Etch Product Group at Lam Research.
Richard A. Gottscho, Judy K. LaCara, James V. Tietz, Lam Research Corp., Fremont, California