Mask program update: Sematech turns its attention to EUV infrastructure
02/01/2003
Though EUV lithography may not be on the ITRS roadmap until 2008 or so, it looks as if it is rapidly starting to become a key focus of International Sematech's mask program. The consortium just announced a development program with Lasertec, Yokohama, Japan, for an inspection tool for multilayer EUV mask blanks. It is finishing up evaluation of proposals for an aerial image measurement system (AIMS) to inspect EUV masks — from multiple suppliers. It will also expand into mask process development for the first time when it starts making EUV mask blanks at its new Sematech North project with University of Albany-SUNY.
The ambitious goal of Sematech's mask program, which takes the largest chunk of the consortium's budget, is to develop the mask infrastructure for a technology node 18 months before the Sematech roadmap volume production date, which itself is two years before the ITRS roadmap's schedule. That means the target for 157nm mask inspection and repair tools is sometime next year — for International Sematech's 2005 target for a technology the ITRS slates for 2007 — and EUV tools only shortly thereafter.
The consortium will work with Lasertec to develop an inspection tool for EUV mask blanks by October 2004, in what Lasertec says is Sematech's first joint development contract with a private Japanese toolmaker. Photomask blanks become a big issue in EUV because they need to be almost entirely free of defects, both on the surface and within the multilayer films that make up the reflective layer. The target is detection of 30nm particles with throughput of an hour/mask blank.
Lasertec says its own EUV mask blank inspection tool announced this summer can currently detect 60nm defects. The company's approach uses confocal optics, essentially screening the reflected light through a pinhole that allows through only the perfectly focused portion, for a clear image of a very thin section of the sample at one spot.
The sections can be built up for a clean 3D image, but of only one point at a time, so the process tends to be slow. Lasertec uses multiple lasers to speed up throughput. The company has done relatively well with its confocal microscopes and inspection tools, even through the downturn. Sales for the fiscal year through June 2002 were some $55 million, and it earned net income of 11% of revenues.
Sematech is seeing surprising interest from toolmakers in making EUV mask inspection gear. Carl Zeiss has been the only supplier of AIMS tools — which can be set up to show the image of the mask pattern that a scanner will print. Sematech's mask program manager Kurt Kimmel says, though, that the consortium is now finishing up reviewing proposals for EUV AIMS tools from multiple candidates, "and with different approaches using different types of architecture."
The 157nm AIMS tool Sematech developed with Zeiss was alpha qualified this summer and is available to Sematech members. The beta version is slated for July 2003, with first right of refusal to Sematech members, as always. The DUV inspection tool the consortium co-funded with KLA-Tencor is now scheduled to ship in April of next year, enhanced for alternating phase shift masks for 193nm, since 157nm has proved so challenging. Sematech did not fund development of Applied Materials/Etec's new scanning AIMS tool that inspects at wavelength, and compares die to die instead of die to databank. "But we supported them by providing expensive test masks," notes Kimmel.
Sematech has budgeted some $160 million to work on making multilayer mask blanks for EUV, at something approaching reasonable cost, using the new UAlbany 300mm cleanroom.
The state of New York will kick in another $210 million. Participants at the consortium's recent EUV symposium voted the problem of making the nearly defect-free multilayer reflective mask blanks needed for EUV as the second biggest roadblock to the technology, surpassed only by the light source.
"It's our first real process development line," says Kimmel. "We'll do defect reduction, cleaning, analysis and such, up to the multilayer — but no patterning."
Though Sematech's e-beam mask program consists of only one researcher, Kimmel says he's getting good results using ultrathin membrane, and was to give a key demonstration at Nikon in Japan late last year. The consortium also funded development of a focused ion beam mask repair tool with FEI for 100nm and 70nm. — Paula Doe, correspondent
TI's foray into FRAMs for embedded NVM
Texas Instruments (TI) recently produced a 64Mb ferroelectric RAM (FRAM) chip (cell size of 0.54cm2) using the company's standard 130nm copper interconnect processing. The effort is the culmination of an internal company evaluation and support from Ramtron International Corp.
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The FRAM concept is old, according to Robert Doering, TI Senior Fellow, silicon technology development. "TI first heard of it when Ramtron visited the company in the mid-80s," states Doering. "The Japanese have also looked into it in recent years."
A team at TI compared a number of exotic memories — MRAMs (magnetic RAMs) and OUMs (ovonics unified memory), and single-electron transistor memories — with not-so-exotic alternatives to embedded memory, and concluded that FRAMs had the desired attributes. The alternative had to be as fast at read/write (R/W) operations as embedded DRAMs and as dense as flash memory, yet have a lower cost than either. The choice also had to be nonvolatile and low power.
"The FRAM can use voltages already on the chip and it has a small bit size, near zero standby, a competitive operating power, and low cost — it requires only two additional mask levels," Doering explains. A standard logic chip (e.g., DSP, microprocessor, ASIC) already has about 20–25 mask levels, without even considering nonvolatile embedded memory. "With some of the other alternatives to FRAM that we studied, the costs might initially seem low, but when you took a look at what it would take to get low power and other features, you would end up with about 7–9 added mask levels."
Another advantage to using FRAMs, according to Doering, is that Ramtron International has had millions of them in the ...field, so there is a history with this technology, unlike exotic alternatives. "Additionally, the materials used — lead zirconate titanate (PZT - for the ferroelectric capacitor) and iridium (electrode material), have been used elsewhere and something is known about them."
Ramtron's very first commercial FRAM became available in 1993, according to company VP of FRAM products, Michael Alwais. At that time, Ramtron had its own foundry but decided to go fabless and made the transition between 1997 and 1998 with Rohm Electronics making Ramtron's FRAMs, as well as its own, in 1998. A second foundry partner, Fujitsu, came on board in 1999; Fujitsu also manufactures its own FRAM products in addition to Ramtron's. Since 1993, Ramtron has shipped about 40 million FRAMs and maintains an interest in both standard and mixed signal memories.
The TI team has targeted an FRAM endurance goal of 1014 write/erase cycles — a requirement that should fit almost all applications in which TI has an interest, particularly hand-held devices. "Typical embedded flash or commodity flash memories meet a requirement for at best 106 write/erase cycles," notes Doering. "For FRAM, 1014 write/erase cycles is very achievable. In regard to yield improvement, the tail of the bit distribution is where we need to do the work."
Doering is referring to the probability distribution that describes the separation between a memory's ability to store a "one" vs. a "zero." The objective is to get the distributions that represent a one and a zero as far apart as possible while also making the distributions themselves very narrow. As a point of reference, cache memory for MPUs (on-board Level-1 cache SRAM) typically requires 1016 write/erase cycles.
The usual process of evaluating new memory options starts with testing individual bits for bi-stable properties, then making small arrays followed by ever-larger arrays. According to Doering, the last step is improving yield and reliability. The TI team will be working with a 64Mb array to study its reliability and to tweak performance, and will continue to shrink the array.
The 90nm node will be next and Doering's best ballpark estimate of its bit size is 0.35µm2. The company expects its first embedded FRAM products to appear at the 90nm technology node. —D.V.
Magnetron sputtering systems enhanced using negatively charged ions
Continuing progress in organic light-emitting diode (OLED) device manufacturing requires that super-smooth indium tin oxide (ITO) thin films be deposited. Plasmion Corp. has what it believes is the answer for such coatings: a way to negatively ionize particles in a plasma in cluster systems and in-line tools.
The invention, called an ion cell, is also expected to play a role as a way to fill Cu trenches, and in the manufacturing of computer hard disks where a thin, hard coating is desired. DWDM filters and mirrors that require smooth, hard, higher conductive coatings are other applications for the technology.
Steve Kim, founder and CTO of Plasmion,as well as inventor of the injector technology that provides the capability to negatively ionizeparticles, explains that the main difference between conventional PVD sputtering and Plasmion's process is that conventional PVD uses positively charged ions and is only good for small areas. In sputtering, positively charged particles tend to go toward the target, not the wafer, but negatively charged particles tend to go toward the wafer in a more controlled manner, according to Kim.
The ion cell uses a cesium discharge to create the negative ion beam. A variety of metal beams can be produced, depending on the target (e.g., C, Si, Au, Cr, Cu, W, B). "It's the controlled energy, moving toward the wafer, that is so beneficial for precise sputtering," explains Plasmion CEO, Jim Ionson.
"The catalytic injector system can be incorporated into a user's current installed base of either in-line or cluster systems — both versions use the same ion cell," states Kim. "The result is a kind of supercharging of the sputtering chamber using the ion cell subsystem and it can be used on large areas." With respect to compounds used for semiconductor and other processes, the top of the cartridge contains a proprietary filter that allows only the most important chemicals from the compound to be ejected.
According to Ionson, the company expects to have 10–15 end users, cutting across all threesegments (semiconductor, FPD, computer disks), in either pre-beta or beta testing by the second half of 2003.
Getting the 193nm shrink out of CD SEMs
Critical dimension (CD) measurement by atomic force metrology (AFM) eliminates concerns about 193nm resist shrinkage that can be problematic when using scanning electron microscopy (SEM), say collaborative researchers at ASM Lithography, Tempe, AZ, and Veeco Metrology Group, Santa Barbara, CA.
It has been widely reported that CD SEM measurements cause 193nm resist features to shrink, violating the fundamental rule that metrology cannot change the feature it is measuring.
Solutions have been reported, including reformulation of 193nm resist and control of (typically reduction of) the electron beam energy used. Often, however, while lower beam energy can help control shrinkage, the impact on a given CD SEM tool's precision is not fully understood.
"With our use of CD-AFM to directly measure 193nm resist surface shape, we see almost no change in the measurement over 50 consecutive measurements, clearly indicating that we are not changing the resist as we measure it. Our comparison with published data shows that successive CD SEM measurements exhibit change with repetitive measurements, especially over the first 20 measurements," says Kirk Miller, applications scientist, Veeco Metrology Group (see figure).
"The significant fact here is that fab engineers can be more confident in a given measurement, particularly when re-measuring a specific site, as is often the case during process development. The potential for demonstrating tool capability is higher, in that you can go back to the same spot and measure it and not change it. This also aids in establishing precision when using a specific fab reference metrology tool or when working with complementary metrology tools," Miller adds.
Veeco's AFM capability yields significantly more information about a CD than what has been conventionally extracted from CD SEM metrology. The former includes top, middle and bottom CD width, depth, two wall angle measurements, and line edge variability. "Increasingly, line edge roughness is crucially important at gate level to produce well-behaved, in the design sense, devices," Miller says.
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