ALD for sub-90nm device node barriers, contacts and capacitors
02/01/2003
Jerry Gelatos, Ling Chen, Hua Chung, Randhir Thakur, Ashok Sinha Applied Materials Inc., Santa Clara, California
Due to shrinking geometries, the ITRS roadmap indicates that ALD processes will be required starting at the 90nm node for a variety of applications: deposition of barriers, nucleation layers, and high-k dielectric materials [1]. The conformal step coverage characteristics and thickness control of ALD make it an ideal technology for applications that require thin, uniform film coverage.
Applications with challenging step coverage requirements include the barrier for Cu interconnect, W nucleation layer, and electrode films in memory structures. With geometries scaling to 90nm and below, these applications require highly conformal and uniform deposition of ultra thin films in increasingly high-aspect-ratio features with potentially rough, nonvertical sidewalls — features that challenge conventional deposition techniques such as CVD and PVD.
ALD technology
ALD relies on self-limiting chemisorption of a reactant molecule (precursor) on the substrate surface. The self-limiting behavior implies that the deposition rate/cycle is determined mainly by the saturation time and is independent of the reactant exposure time after saturation. Surface saturation characteristically occurs very fast, with sub-second timing. For example, in the ALD TaN process, the (tantalum) precursor saturates within 0.5 sec for an average deposition rate of ~0.5Å/cycle. The saturation time for the ALD TiN and ALD W processes are even shorter, on the order of 0.2 sec.
Because of their self-limiting attribute, ALD reactions in general can occur at a lower temperature than conventional thermal CVD, enabling integration with low thermal budget process flows. For example, with ALD TiN, the substrate temperature can be reduced by more than 100°C compared to a conventional CVD process. The ALD TaN films for Cu barrier application are deposited at temperatures of 250–300°C, and are thus compatible with Cu low-k integration.
The engaging ALD precursors are required to be highly reactive for a self-limiting surface reaction mechanism, and they produce volatile by-products. Deposition should occur predictably on all targeted surfaces, both metal and dielectric in the case of barrier films, at the same rate. Further, the reaction must take place within the thermal budget constraints of the pertinent application.
ALD films typically behave differently than thicker films because they are so thin. Issues such as adhesion, interface structure, and composition affect overall process flow performance and must be verified with this process technology.
 Figure 1. ALD barrier maintains the crystalline order on Cu, enabling epitaxial growth of the Cu via on the Cu line beneath for low via resistance. |
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ALD tantalum nitride
One of the most critical applications for ultrathin ALD films is for the barrier in Cu interconnect structures. As Cu linewidths are reduced below 90nm, a highly conformal barrier layer that provides an effective diffusion barrier between Cu and the low-k material with very low barrier thicknesses (~10–20Å) is required. This ensures the fraction of higher resistivity barrier material is kept to a minimum within the Cu interconnect for overall low line resistivity while line-widths are reduced [2].
Ultrathin TaN films, deposited using ALD techniques, can provide 100% step coverage with <15Å thickness and nonuniformity of <3%, 1s on 300mm wafers. Further testing of diffusion barrier properties shows that even 10Å of ALD TaN is a better diffusion barrier than 50Å of PVD TaN barrier. (It is instructive to note 50Å of PVD barrier on a via sidewall would require ~300Å of PVD deposition on the field and the lines.) These results suggest that ultrathin ALD TaN barrier films can enable the line resistance scaling required for Cu interconnects at the 65nm device generation and beyond.
To verify the integration of the ALD TaN barrier in Cu metallization, electrical testing was conducted on dual level metal interconnect structures. Using ALD TaN, via chains and line structures with two ILDs were fabricated: fluorinated silicon dioxides (FSG) and low-k carbon doped oxides (CDO). ALD TaN reduced via resistance up to 40% and line resistance up to 25%, providing a significant reduction in RC delay in interconnects.
While the line resistance reduction could be attributed to the reduced barrier film thickness, the via resistance reduction observed was much higher than anticipated. TEM analysis of the electrical structures provides an explanation. As seen in the TEM image in Fig. 1, the low via resistance observed for the ALD barrier process is attributable to the fact the ultrathin ALD TaN barrier (~10Å), while an amorphous film on a dielectric, maintains crystalline order on Cu to enable epitaxial growth of the Cu via on the Cu line underneath. In thermal stress tests with the FSG and CDO dielectrics, results showed no via resistance or yield shift on a 3.4 million via chain after 168 hrs stressing at 175°C for 10Å barrier films. The analysis of the thermal stress data suggests that the epitaxial growth of the Cu in the via on the Cu line below is essential for good stress migration performance.
In addition to enabling scaling Cu interconnects to 65nm and beyond, the ALD TaN barrier has a lower cost of consumables (<50%) compared to PVD TaN deposition. The ultrathin barrier process can enable a one-step CMP process that will further lower the overall COO.
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ALD tungsten
Tungsten contact plugs are commonly deposited by CVD from the reduction of tungsten hexafluoride (WF6) with hydrogen. Presently, a CVD nucleation step using WF6 and silane (SiH4) is required to ensure uniform deposition of the tungsten bulk fill layer and to act as a fluorine barrier for the bulk fill reduction reaction. A standard liner/barrier for W plug fill applications is PVD Ti/.MOCVD-deposited TiN, which is typically plasma treated after deposition.
A result of this post-treatment is that these films vary in thickness and density depending on whether the film is on the sidewalls or bottom of the contact. Integrating W with this and other TiN liner/barrier films to maintain perfect fill and low plug resistance for sub-100nm requires pioneering improvements in the nucleation layer, especially for high-aspect-ratio structures in DRAMs and embedded DRAMs.
ALD technology ensures contact reliability for very aggressive structures. ALD can be used to advantage to deposit the W nucleation layer because it is highly controllable and deposits uniformly within very high-aspect-ratio vias. After nucleation, the uniform nucleation step coverage ensures a wide process window for the subsequent void-free via fill of the tungsten plug using conventional CVD. We have developed a process for tungsten nucleation using WF6 as the tungsten precursor and a diborane as the reducing agent that demonstrates superior properties compared with conventional silane reduction. This diborane process integrates well with MOCVD liner/barrier layers and results in dense, core-free tungsten plugs [3].
Operating within the ALD regime of low pressure allows very low flows of reactant gases, while maintaining the ALD satura-tion regime. Each reactant exposure rapidly saturates the surface, enabling both a very short exposure time and short purge times [3]. An automated high response gas injection system and fast response valves support process steps as short as 100 msec. The substrate temperature window is 300–350°C with 2.5–3.0Å/cycle growth rates .
ALD tungsten can provide 100% step coverage for aspect ratios greater than 20:1. The ALD tungsten resistivity is 150µW-cm, comparable to 160µW-cm reported for amorphous CVD tungsten films [4]. The stress for a 250Å-thick film, measured with a stress gauge, is 8 ¥ 109 dynes/cm2 (tensile). The ALD layer sheet resistance within-wafer uniformity was 2.0%, 1s, and the wafer-to-wafer uniformity was 1.3%, 1s as measured with a four-point probe (Fig. 2).
The fluorine (F) by-product content of the nucleation layer can be reduced with the ALD W process. This is a concern in tungsten because fluorine can degrade the underlying TiN barrier layer and attack the titanium liner. In ALD deposition, excess reactant and volatile byproducts are effectively removed during the purge steps, and as a result the fluorine content in ALD tungsten films as measured by SIMS is 7 ¥ 1017 atoms/cm3, which is 10¥ lower than in CVD tungsten films.
 Figure 3. TEM images show complete contact fill with ALD W and CVD W a) and prevents attack on sensitive corners for thin IMP Ti/MOCVD TiN layer (b, c). |
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Integration of ALD W nucleation and W CVD
W plug fill performance can be further enhanced by optimization of the contact plug integration with PVD Ti/MOCVD-TiN liner/barrier film. The barrier properties of the ALD tungsten film enable both the ALD W and the MOCVD TiN liner/barrier thicknesses to be reduced to ≤50Å (Fig. 3), providing scaling to sub-90nm.
The film properties of a 2000Å ALD W/CVD bulk W stack were compared with those of a 2000Å film stack prepared by conventional CVD. Both stack films had a similar resistivity (~11µW cm), stress (~1.5 ¥ 1010 dynes/cm2, tensile), and uniformity (<2% 1s). The reduction in the fluorine concentration at the interfacial area observed in the ALD nucleation film is maintained after complete contact fill, and is approximately 4 ¥ 1020 atoms/.cm3, compared to 1 ¥ 1021 atoms/.cm3 associated with via fill integration for conventional W nucleation layer. This reduction in F concentration verifies that the ALD nucleation process is more effective than CVD tungsten nucleation as a barrier to fluorine diffusion.
ALD titanium nitride
An ALD titanium nitride process has been developed using titanium tetrachloride (TiCl4) and ammonia (NH3). The deposition temperature of ALD TiN, 450–550°C, is significantly lower than the typical 600–680°C deposition temperatures for TiCl4 CVD TiN. X-ray diffraction (XRD) measurements show that the ALD TiN film is predominantly <111> phase mixed with <200> and <220> phases. For comparison, CVD TiN is <200> phase and PVD TiN is <111> phase.
The grain size is ~100Å for a deposition temperature of 500°C. The chlorine content of the ALD TiN film deposited at 500°C is <1 atomic % compared with 5 atomic % for a CVD film grown at the same temperature. The lower content of chlorine in ALD TiN leads to a film resistivity below 150µW-cm, even when grown at a low temperature. The step coverage of ALD TiN is >90% for a 130nm-wide trench with an aspect ratio >50:1.
Conclusion
ALD has the capability to deposit ultrathin (~10Å or more) conformal layers within structures <200nm in width with depth/width aspect ratios approaching 50:1. ALD thin films increase the process windows for subsequent steps, enable scaling and better composition, and reduce thermal budgets. An ALD tungsten nucleation process has been successfully integrated into tungsten via stacks.
Development of an ALD TiN process has been advanced to meet the high aspect ratio and surface morphology needs of TiN capacitors. Also, a process for ALD TaN barrier films for copper interconnects has been developed that provides significantly lower via and line resistance than PVD Ta (N) barriers. Electrical testing verified thermal and stress reliability with low-k dielectrics.
Acknowledgments
Applied Materials technical staff members Nirmalya Maity and Cheryl Knepfler contributed to this work.
References
- International Technology Roadmap for Semiconductors: 2001, (http://public.itrs.net/Files/.2001ITRS/Home.htm), Interconnect, pp. 1, 5–6.
- Krishna Saraswat, Pawan Kapur, "Scaling Induced Challenges with Metal Interconnects," presentation, Dept. of EE, Stanford U, Sept. 30, 2002.
- Michael Yang, et al., "Atomic Layer Deposition of Tungsten Film from WF6/B2H6: Nucleation Layer for Advanced Semiconductor Devices," Proc. of the Annual Meeting of the AMC, 2001.
- K.-M. Chang, I-C. Deng, H.-Y. Lin, "Suppression of Fluorine Penetration by Use of In Situ Stacked Chemical Vapor Deposited Tungsten Film," J. Electrochem. Soc., 146(8), pp. 3092–3096, Aug. 1999.
Jerry Gelatos received his PhD in physics from the Univ. of Oregon. He is director of the Contact Metallization Div. at Applied Materials, where he is responsible fortungsten and titanium and titanium nitride CVD products. Prior to Applied Materials, Gelatos spent seven years working on metallization technologies at Motorola. Contact [email protected].