Lithography Part I of a series
02/01/2003
Michael Fritze, Brian Tyrrell, Advanced Silicon Technology Group, MIT Lincoln Laboratory, Lexington, Massachusetts
overviewAs optical lithography extends further into the sub-wavelength regime, advances in resolution enhancement technology are becoming critical to the survival of Moore's Law. These techniques serve as system drivers for many areas of the semiconductor infrastructure, including advanced mask fabrication processes, new electronic design automation software tools, and stepper optimization. Economic considerations may lead to the adoption of different resolution enhancement approaches to satisfy the contrasting needs of high-volume applications such as DRAMs and MPUs and low-volume applications, such as ASICs, for which nonrecurring costs cannot be easily amortized.
Beginning in 1997, with the 180nm device technology node, the semiconductor industry has been applying optical lithography to feature sizes smaller than the exposure wavelength. Despite the recent introduction of a new exposure source at 193nm and the anticipated introduction of 157nm-based systems, this sub-wavelength gap has continued to grow. In fact, the requirement of sub-wavelength lithography is a direct consequence of Moore's Law itself. Consider the classic lithography equations:
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where l is the wavelength of the illumination, NA is the numerical aperture of the lens, and k1 and k2 are process constants. It is immediately apparent that an exponential reduction in feature size cannot possibly be accommodated by what has roughly been a linear reduction in wavelength. Scaling of NA, k1, and k2 are also essential. Numerical aperture has been asymptotically reaching a practical limit of about 0.85, although there is recent research in extending this limit using liquid immersion methods [1]. Resolution enhancement technologies (RETs) are aimed at improving k1 and k2 in at least a sublinear manner, with k1 approaching a theoretical limit of 0.25 (for dense L/S patterns). Currently k1 ≈ 0.4 and k2 ≈ 1.0.
If history is any guide, next-generation lithography (NGL) methods based on extreme-ultraviolet (EUV) or electron projection lithography (EPL) will not relieve this burden on optical lithography any time soon. Many commentators have observed that over the past decade or so, annual technology roadmaps have almost consistently predicted that optical lithography would give way to next-generation techniques approximately seven years from their respective dates of publication. Even if NGL technologies become available by the end of this decade, there is a serious concern about their potential cost and the time required for insertion of an entirely new lithography infrastructure into commercial use [2].
Current state-of-the-art design rules are at the 130nm technology node with minimum MPU gate lengths in the 60–70nm size range. Development work is ongoing at the 90nm technology node, in which minimum gate lengths will range from 40–50nm. These features will be imaged using a combination of 193 and 248nm optical lithography tools.
A key question for the future is how far optical lithography can be extended using RET. Can 193nm be pushed to the 70nm node, or 157nm be extended to the 50nm node? Clearly, the answer to this question will depend heavily on the cost-effectiveness of optical RET. Concerns are already being expressed regarding the explosion of reticle costs for advanced technologies [3]. There is also the concern of how RET methods may impact the design cycle with the introduction of new design rules, techniques, and challenges [4].
 Figure 1. Schematic illustration of typical OPC strategies. |
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Review of current RET methods
The most commonly used optical RET today is optical proximity correction (OPC). Proximity correction has been used informally for many years, and recent developments have introduced sophisticated algorithms and electronic design automation (EDA) software to formalize this process [5].
The basic goal of proximity correction is to correct for the low pass filter effect that a projection lithography system has on the spatial frequencies of a desired pattern. The loss of high spatial frequencies causes undesirable effects such as corner rounding and line end shortening. OPC mitigates such effects by adding features to the mask such as mousebites, hammerheads, serifs, and scattering bars (Fig. 1).
In addition to correcting for high spatial frequency loss, OPC also mitigates iso-dense proximity effects. This is accomplished by making isolated lines, which typically have the smallest depth of focus (DOF), look optically dense; generally, this is accomplished by the addition of assist features such as scattering bars [6].
The challenge in implementing OPC is in construction of algorithms that can automatically create, for a given representation of a desired pattern, a mask design that will suitably produce that circuit in silicon. During this processing of a circuit layout, data volume must be kept manageable, and processing time must be kept reasonable. Rule-based, model-based, and hybrid OPC approaches are available [7].
 Figure 2. A 25nm gate length circuit fabricated by the double-exposure PSM method [28]. |
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In a rule-based OPC algorithm, a set of geometric functions, or rules, are applied to an input layout to produce an output mask design. In a model-based approach, an optical simulator is used to provide a feedback path to the mask generation algorithm. A hybrid approach attempts to take advantage of the speed of rule-based OPC with the accuracy of model-based OPC to achieve an optimal result.
In addition to the computational challenges, the mask design must be manufacturable. Maskmakers are currently required to fabricate feature sizes of the same order as the device fabrication engineer, without the benefit of a 4–5¥ reduction factor. The requirements for sophisticated OPC corrections have helped drive the transition to more precise and costly dry etch processes in maskmaking [8].
OPC methods typically increase process latitudes and yields for sub-l processes, but no dramatic improvement in resolution has been possible using these technologies. In addition, OPC masks are becoming increasingly complex and expensive with data volume and data management emerging as major challenges [9].
Off-axis illumination (OAI) is a desirable RET since it is fairly simple to implement. Most modern steppers offer easily adjustable illumination types, including annular and quadrupole sources. Recent work has explored the applicability of double-dipole image decomposition [10]. Custom illumination apertures can also be designed for specific patterns and easily installed in a stepper [11]. OAI works by moving higher-order diffraction components, which would normally be lost, into the lens capture field [12]. Image modulation is therefore possible for spatial frequencies normally not resolved, at the expense of contrast since some of the light is lost.
OAI is particularly useful for dense regular patterns where a significant increase in process latitude can be obtained. The use of pattern-specific custom illuminations can dramatically improve imaging. Unfortunately, OAI typically increases the iso-dense proximity effect, thus requiring the use of OPC for imaging arbitrary patterns through pitch. As a result, OAI is rarely a stand-alone solution to RET. Rather, it provides a means of further improving upon the benefits achieved through the use of OPC.
The use of interference effects to image small dark lines in optical lithography, or phase shift masks (PSMs), was first proposed in the early 80s [13]. The advantage of this method is that dramatic resolution enhancement is possible (< l/2 for MPUs) with excellent process latitude, i.e., a large DOF and wide exposure latitude (EL). The mask error enhancement factor (MEEF) is also significantly reduced, thus easing some mask fabrication concerns [14]. A wide range of PSM methods have been developed to define the deep sub-wavelength features currently required of optical lithography.
Weak PSM methods, which include attenuating PSM (a-PSM) and chromeless phase lithography (CPL, also known as CLM), rely on three diffraction orders to form an image on the substrate. Strong PSM methods allow for much more dramatic resolution enhancement since only two diffraction orders must be within the lens capture field. The primary disadvantage to strong PSM is that multiple exposures are necessary.
The major challenges in the area of PSM lithography include increased manufacturability since the fused silica mask material needs to be precisely etched, inspected, and repaired. There is also the image intensity imbalance problem brought on by the 3-D topography of this type of mask [15], although recent work proposes a solution to this problem [16]. One of the most common PSM implementations is a double-exposure method, which requires an automated decomposition of the desired pattern into two masking layers, a PSM and a trim mask [17]. The EDA infrastructure is developing to facilitate this process, but there is still the very significant problem of converting legacy designs efficiently. In new designs targeted toward PSM-based fabrication, "RET aware" design rules are followed from the start of the layout process, reducing the burden on post-processing algorithms.
 Figure 3. Silicon-on-insulator transistors with gate lengths in the 90–9nm size range fabricated using double-exposure PSM lithography [29]. |
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Challenges of optical RET
The most serious challenge facing RET methods is not technical but economic. Mask fabrication complexity is leading to very high mask costs [3]. For example, the issues of inspectability and repair have not yet been fully resolved for PSMs, so mask yield can be quite low. Also, unlike most fabrication-related challenges, RET methods have a direct impact on the design process, which already dominates the nonrecurring cost of IC components. New design rules are clearly required to fully utilize the benefits of RET. This poses a problem for the RET conversion of legacy designs. The specific RET-aware design rules are strongly dependent on the type of RET chosen, dramatically reducing the portability of existing IP. This has led to a reluctance in the design community to fully accept RET-enabling design rules.
Cost amortization is another key issue in the future development of RET and will likely lead to the choice of different RET methods for particular applications [18]. For high-volume applications such as DRAMs and MPUs, nonrecurring costs are easily amortized over the production volume, thus making custom RET and expensive masks economically viable.
Moderate to low-volume applications such as application-specific integrated circuits (ASIC), systems on a chip (SOC), custom RF and analog circuits, and photonics devices are facing increasing difficulty in justifying the cost of RET methods [19]. In fact, there has been an alarming decrease in ASIC starts lately, driven partly by high nonrecurring costs [20]. The development of a cost-effective RET approach for low-volume applications is a key challenge for the future.
 Figure 4. Schematic illustration of the GRATEFUL dense-only lithography method [27]. |
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High-volume RET
The DRAM community has been one of the first to adopt RET approaches involving custom crafting of masks. For this type of application, high mask costs and design complexity can be amortized. The combination of OPC and OAI has been found particularly useful for DRAM applications due to the dense regular nature of the involved patterns [21]. The challenge here is to add just enough pattern complexity to achieve the desired result, thereby minimizing data size and mask fabrication complexity.
The most common PSM-based RET in use today is based on double exposure [17]. This involves the decomposition of the desired pattern into two masks, a dark field PSM and a bright field binary trim mask. The technique has been found to work well for partial (gate only) scaling applications. Dramatic resolution enhancements have been reported for gate levels (Figs. 2, 3) [22]. An additional advantage of all strong PSM methods is the significant reduction in the MEEF [23]. Recent work has extended the double-exposure PSM approach to fully scaled designs at the 130nm node and below [24]. Future developments in strong PSM will need to address the increasing complexity of PSM and trim masks, as well as the optimization of the image decomposition algorithm.
CPL — the recently developed alternative to strong PSM — is an advanced weak phase shift method based on chromeless masks [25]. The advantage of this method is that it requires only one exposure per level, which is important for the throughput considerations that dominate at high production volumes. CPL, however, does share many of the mask complexity and layout issues inherent in strong PSM approaches.
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Moderate-/low-volume RET
As feature sizes continue to scale, the moderate- to low-volume production of ASICs, SOCs, custom RF and analog circuits, and photonics devices will not be able to accommodate the high nonrecurring cost of RET-based methods [19]. Because of this dilemma, different approaches to RET are being contemplated for these cases.
Over the past several years, there has been a growing interest in the use of relatively simple feature "templates" to implement cost-effective RET. The use of simple PSM gratings together with a multiplexed trim exposure has been explored [26]. The concept of simple, re-usable PSM template masks together with the appropriate trim customization has also been discussed [16]. These approaches have been further extended through the use of multiple resist layers with independent imaging (Figs. 4, 5) [27].
There are a number of advantages to these methods. The fine features on the PSM templates are generally of simple geometries, thus easing mask fabrication and inspection complexity. By re-using the more expensive PSM templates and performing customization with a far less expensive binary trim mask, mask costs may be reduced tremendously [16]. For cases in which the PSM templates are dense patterns, the need for complex OPC is greatly minimized if not eliminated entirely, since without isolated features on the template mask, there is no possibility of iso-dense bias [27]. Design optimization time is also reduced since the templates can be pre-characterized for RET compliance [27].
These advantages come with some trade-offs. All fine features must be placed on the PSM template locations during the design process. Some flexibility in layout is thus lost in exchange for far lower mask costs and shorter design RET optimization time. Some process complexity is also added as these methods require multiple exposures or resist layers. Such trade-offs are not necessarily severe; in fact, multiple exposure PSM methods are being readily accepted for high-volume applications today. In addition, recent work has shown that ITRS roadmap densities can be achieved for many common types of designs even when PSM grating templates are used [27]. The cost savings provided by such methods have been shown to be compelling for low-volume applications [27]. These economic drivers may lead to the emergence of a design option that lies between the FPGA and the ASIC in its cost/performance ratio.
Conclusion
Numerous competing approaches to RET have recently come into use. As with any new sub-field of technology, some of these will find a niche, and others will fall by the wayside. The drivers for this evolution will be both economic and technical. Economic drivers will likely lead to a divergence in the paths of RET development, with high- and low-volume applications taking different approaches. Optical lithography can be expected to carry Moore's Law to the end of the decade, with k1 approaching the theoretical limit thanks to these RET technologies.
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Michael Fritze received his BS in physics from Lehigh University and his PhD in physics from Brown University. He is a staff member in the Advanced Silicon Technology Group at MIT Lincoln Laboratory, 244 Wood Street, Lexington, MA 02420-9108; ph 781/981-2626, fax 781/981-7889, e-mail [email protected].
Brian Tyrrell received his BSE in electrical engineering from the University of Pennsylvania. He is an associate staff member in the Advanced Silicon Technology Group at MIT Lincoln Laboratory.