One nano step toward efficient LED lighting
01/01/2003
Engineers at Kopin Corp. (Taunton, MA) are using nanotechnology (patent pending as NanoPockets) to produce "CyberLites" — blue light-emitting diodes (LEDs) smaller than a grain of sand (Fig. 1). The new LEDs are as bright as 3.3V commercially available devices, yet can be driven by <2.9V (using 20mA of current) and still have 100 mC brightness. In addition, CyberLites have achieved ESD resistance >4000V compared to ~2000V resistance with commercially available LEDs; high ESD resistance is critical for industrial applications.
This work was done in cooperation with Jagdish Narayan of North Carolina State University and director of the NSF Center of Advanced Materials and Smart Structures.
"Getting below 3V has been a scientific hurdle for nearly a decade," said Kopin Chairman John C.C. Fan. "It took a new way of thinking to overcome this challenge. With further development, we can approach the holy grail of using these solid-state sources for general lighting. In addition, this is an important first step in the commercialization of nanotechnology."
 Figure 1. Kopin blue CyberLite on a US dime. |
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NanoPockets is based on Kopin's patented wafer engineering process, already being used by the company for displays and HBT transistors; this process significantly reduces the number of natural atomic level defects when different semiconductor materials are combined. CyberLites are fabricated on gallium nitride grown — via organometallic chemical vapor deposition — on low-cost aluminum oxide ("sapphire"). The process provides confinements ("NanoPockets") for production of light away from defects (Fig. 2). The nanostructures, which are naturally formed as a result of internal strains, are spaced less than the separation of material defects, such as dislocations.
Fan says, "The next step is achieving mass production. Although this is always the toughest part, we believe we can move CyberLites into large-volume production for the mass market. We have already begun shipping evaluation samples of CyberLites to prospective customers."
A blue CyberLite can be combined with yellow phosphor to create a white LED. Blue and white CyberLites are ideal for compact battery-powered portable light-using devices, such as wireless phones, games, camcorders, cameras, laptops, and PDAs. The high-brightness LED market is already $1.2 billion, and it is expected to grow to more than $3 billion by 2005, according to Strategies Unlimited.
Technique gives thin metals suitable for MRAMs
A team of National Laboratory scientists has developed and patented a technique that can deposit flat, ultrathin metallic layers on very thin oxide layers, circumventing the tendency of metal atoms to cluster in "islands" when deposited on oxide surfaces. The new method achieves crystallinity with only a few atomic layers. These findings may have the most immediate bearing on magnetic tunnel junctions used in magneto-resistive random access memory (MRAM), which are evolving for nonvolatile computer-memory applications. Beyond MRAM, there is a broad range of potential industrial applications.
 The presence of hydroxyls is at the root of a new technique that can deposit flat, ultrathin metallic layers on very thin oxide layers |
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Evolution of this new technique goes back to 2000 when Sandia Laboratory, Albuquerque, NM, solid-state theorist Dwight Jennison approached Scott Chambers, a chief scientist at Pacific Northwest National Laboratory, Richland, WA, with a theory that the presence of hydroxyls would enhance the binding of metals to oxide surfaces. Jennison calculated that certain metals would form flat films on sapphire. Using a special synthesis technique that he created, Chambers and postdoctoral fellow Tim Droubay produced an atomically flat film of cobalt on hydroxylated sapphire. They found, as Jennison had suspected, that the cobalt accumulated in layer-by-layer fashion, rather than clustering.
"Cobalt's interaction with oxide is so weak that it would normally ball up when deposited," says Jennison. "However, by changing the surface of the oxide, Scott discovered that cobalt atoms can cause the release of a hydrogen gas molecule and the cobalt atoms then become oxidized themselves and end up strongly bound within the top layer of the oxide. These are anchors."
These metal atoms, embedded at scattered points within the top layer of the oxide, amount to about one anchor for every 10 oxygen atoms in the top layer. The anchoring atoms bind other metallic atoms to themselves and to each other just above the oxide surface, forming a crystalline metallic layer (see figure).
Computer-based calculations behind this work provided insight into what reaction is taking place, where it occurs, the energy barrier for it to happen, and the time needed for completion vs. the time for arriving cobalt atoms to lose energy while in contact with the surface. If the reaction occurred slowly, the rapidly diffusing cobalt atoms would first find a growing island. However, because hydrogen molecules are being made, the reaction can be on the order of tenths of a picosecond. This is well before the arriving cobalt atoms can assume the temperature of the substrate.
While experiments were done using cobalt, Jennison's calculations predict that the method also would be effective for iron and nickel, two other metals under consideration for MRAM, as well as metals such as copper, ruthenium, and rhodium. The latter two have applications in catalysis. Catalysts are involved in approximately two-thirds of the gross domestic product of the United States, particularly for production of oil.
"Many advanced technologies rely on strong interfaces between metals and oxides," said Chambers. "These findings may provide the molecular insight industry needs to create better materials for microelectronics and sensors." The new technique uses conventional wafer fabrication equipment. "For industry, a solution may be as simple as exposing the thin aluminum oxide films to a low pressure of water vapor before adding a final cobalt layer," Chambers said. The entire process may be done at room temperature.
Leapfrogging Moore's Law via IC design
Infineon Technologies, Munich, Germany, has a new IC design technology — dubbed MyVP or My Virtual Processor — that "jumps over the limitations of Moore's Law" without reducing transistor size or changing wafer-processing technology. Briefly explained, MyVP technology is based on a series of innovations that make it possible to use multithreading (a technique developed for high-performance computers) in embedded processors, while maintaining or improving real-time determinism (i.e., predictable execution of certain tasks within critical nanosecond time spans), which is required for embedded systems.
This architecture can increase tenfold the performance of embedded processors used in mobile phones, PDAs, computer peripherals, automotive electronics, etc. For example, consider an application where a 400MHz processor is paired with low-cost 40MHz flash memory, a common tradeoff used with consumer electronics to make them cost-competitive. Conventionally, the processor can waste 90% of its time waiting for instructions from the slow memory. With MyVP, an embedded processor acts like multiple separate "virtual" processors; when one is forced to wait, others take over efficiently, using 100% of the chip's calculating resources.
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The overall benefit with MyVP is that designers can reduce system memory cost while actually increasing performance; new multimedia features can be added inexpensively. Conversely, they can also design with lower-speed processors that use MyVP technology to improve battery life, all without any other changes in design.
Infineon is putting this technology into a new 32-bit microcontroller to be introduced in mid-2003. The company also plans to actively license MyVP technology. — P.B.
Local Euros kick-start 300mm IMEC fab
Calling it a "platform," IMEC has committed to building a 300mm silicon research foundry (see figure) that will address process research at least two generations ahead of current industry manufacturing. The new fab will be built next to IMEC's existing facilities in Leuven, Belgium, and should be fully operational by 2004.
The initiative will serve several as-yet unnamed chipmakers and development organizations worldwide. With IMEC still seeking major partnerships, a key step in this project is the infusion of 37.18 million euros from the local Flemish government, enough funding to begin cleanroom construction.
 IMEC's proposed 300mm research foundry. |
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Addressing the incentive behind this program, IMEC's VP of silicon process and device technology, Luc Van den hove, says, "With the combination of accelerating research and the introduction of 300mm wafers, very few companies will be able to afford a full process research facility. Moreover, industry has to move ever faster from one technology node to another, resulting in a serious risk that progress will slow because of a lack of fundamental understanding of all aspects of the technology."
Building on established IMEC strengths, the new 300mm fab will target flexibility, will operate at ultrashort cycle times via single-wafer processing, and will be built around the world's most advanced 157nm and EUV lithography clusters; IMEC has close ties to ASM Lithography, Veldhoven, The Netherlands. Van den hove defines the facility's flexibility as the ability to introduce many new materials without cross-contamination problems. Work at this facility will probably include some single-wafer-to-batch process comparisons. In addition, engineers there will be demonstrating novel device architectures.
Prof. Gilbert Declerck, president and CEO of IMEC, says, "Within this research platform, IMEC will continue its current successful business model, based on a sharing of cost, risk, talent and IP. Strategic long-term partnerships with a core set of equipment suppliers and major IC manufacturers will be set up to carry investments. The initial funding from our local government is a strong signal from the Flemish Government to stimulate further investment by international industrial partners and the European Commission in this new initiative."
This new lab will also allow IMEC to free up space in its current 200mm cleanroom to perform research in a broad range of nanotechnology and MEMS domains. This research is important in preparation for the post-silicon era and will have numerous applications in new industries and spin-offs.
193nm phase-shift litho delivers 30nm gates
A group of engineers from Toshiba Corp. and Sony Corp. (Yokohama, Japan) has revealed "first-reported" 65nm CMOS technology. They developed this technology for high-performance system on a chip (SOC) applications, especially for broadband core chips (i.e., ultrahigh-performance transistors and embedded high-density memories). This was the subject of a key paper presented at the recent 2002 International Electron Devices Meeting (IEDM) in San Francisco.
Key accomplishments of this process technology are impressive 30nm logic gate lengths, 0.6µm2 embedded SRAM cells, and 0.11µm2 embedded DRAM cells. The device uses a 6.5µm deep trench capacitor, providing 20fF storage node capacitance.
The MOSFETs in this technology have high nitrogen concentration plasma nitrided oxide gate dielectrics to suppress gate leakage current (~1.5 orders of magnitude reduction in leakage current compared to SiO2). In addition, they use a polysilicon-SiGe gate electrode; this material is pre-doped n+ using a relatively low-activation spike rapid thermal anneal, to suppress gate electrode depletion. Nickel salicide is applied to the gate electrode and source-drain regions for low resistivity and to reduce junction leakage current.
The all-important lithography was done with high-NA 193nm exposure using Levenson phase-shift masking and a resist slimming process combined with non-slimming trim masks.
The process ends with 180µm pitch copper interconnects and 2.7 low-k dielectrics, a BEOL process capable of up to 11 metal layers.