Perspectives
01/01/2003
SST editors ask ITRS authors about tough roadmap problems
At the end of 2002, the authors of the International Technology Roadmap for Semiconductors (ITRS) revised the roadmap's tables, which indicate future problems the semiconductor industry must address. After the tables' release, Solid State Technology posed this question to various chairs of ITRS technical working groups: What are particularly troublesome, lingering, (or new) problems for the industry that seem to defy solution or go ignored? Two responses are below; three more will appear in February.
Modeling and simulation
Shrinking features and more complicated device architectures require increased, focused efforts on modeling and simulation to meet targets in terms of cost reduction. Physically motivated phenomenological models must be increasingly replaced by predictive physical models, including first-principle, atomistic, and quantum approaches. These must include additional variables influencing processing and device performance, such as stress in all process steps, various contaminations, and fluctuations. Hierarchical simulation methodologies to integrate all levels of simulation — from process through device, circuit, and chips, to package — will become mandatory. Moreover, the introduction of new materials requires a considerable broadening of activities.
Altogether, these requirements are serious scientific challenges that can only be met by a consolidated effort from industry, software houses, and applied and basic research. Furthermore, highly interdisciplinary work between different domains of science is indispensable. The key problem now is how to make this work happen and optimize its direction and its results. Based on the ITRS results, more detailed requirements must be worked out between industry and research. Then, focused research must be started in time, which in many cases means several years before the required industrial use of the results. Due to the precompetitive nature of such work, it must be carried out by industrial consortia, research institutes, or universities.
In any case, this requires the timely availability of the necessary resources and the organization of an efficient cooperation between all parties involved — from the industrial specification, through basic and applied research work, to implementation of results in commercial tools, and their evaluation and application. Moreover, it requires cooperation between different scientific domains. This is especially important because, traditionally, the direction of research is frequently based on the equipment and expertise available at research organizations, and on their individual prospects to get their work funded, rather than on consolidated worldwide requirements.
If at all possible to implement, and similar to the need for consolidated worldwide industrial specifications defined by the ITRS, a consolidated and worldwide funded research action plan is needed to ensure that the required work can be done efficiently, in time, and with optimum use of resources.
By: Harry J. Levinson
AMD
Lithography
In lithography, the lack of a known path to a solution is quickly apparent for the control of critical dimensions, particularly for microprocessors. Several manufacturers of microprocessors have insisted that gate length must be controlled to ±10% (3s) of the final dimension to meet customer requirements, such as processing speed, while some other companies have expressed concern that the semiconductor lithography industry will not be able to meet the challenge cost-effectively. There has been an enormous acceleration in the rate at which gate length has decreased over time, compared to the expectations of earlier roadmaps. It is quite possible that the final gate dimension has accelerated faster than any other quantity in the ITRS. The consequences of this acceleration have been manifested most clearly in the area of dimensional control.
As a result, several aspects of lithographic technology are becoming stressed. Processes involving binary masks will require exceptionally tight dimensional control on the mask because of the large mask error factor associated with such processes. On the other hand, alternating phase-shifting masks can be used for achieving smaller mask error factors, but these masks are more difficult to make. Either approach presents serious challenges for maskmaking. As final gate dimensions fall below 50nm, the dimensional control requirements become comparable to existing resist line-edge roughness. While more needs to be done to assess the impact of line-edge roughness on device performance and metrology, some improvement in this key resist parameter will most likely be needed.
There is also a need for very little across-wafer dimensional variation, which has contributions from resists, resist processing, and the exposure tool. The exposure tool also contributes to linewidth variation through lens aberrations, which will cause gate dimensions to vary across each exposure field. The acceleration in gate length shrinking has also led to concerns about the ability to measure gate dimensions in the future, and there may not be adequate measurement resolution to address the issue of line-edge roughness.
There are many challenges facing lithographers, such as aggressive pitches and the associated overlay requirements. Of all of the difficulties that lie ahead, none of these appears to be as formidable as gate dimensional control for microprocessors. This is the biggest current and future challenge for lithography.
By:Jürgen Lorenz
Fraunhofer Institut