ALD Special Report: Where's the metal?
01/01/2003
overview
This report covers traditional ALD applied to BEOL and FEOL applications, as well as process technology evolving into ALD. Even with all the progress at the leading edge of ALD, however, at least one researcher is looking for more metal — specifically, Ta ALD now, and Cu ALD later.
Most technologists describe atomic layer deposition (ALD) as a sequence of self-limiting surface reactions at low temperature, resulting in a monolayer of deposited film. But there are some variations also being explored. The semiconductor industry commonly develops new technology by adapting and modifying existing equipment and methods to tackle new challenges, rather than making radical changes. Some of this is happening as toolmakers wrestle with the low throughput of traditional ALD.
ALD promises an exceptionally clean process technology at low temperature that could provide conformal and uniform coatings with extendibility to several nodes — for at least 10 years or more according to some (see table on p. 36 and "The market outlook" on p. 38). Leading-edge IDMs and foundries are looking to ALD to address the challenges associated with capacitors, spacers, thin gates, Cu barrier/seed layers, and metal contacts.
ALD is also a stable process over a wide temperature window and is self-limiting. As a result, there is a linear relationship between thickness of the layer deposited and the number of deposition cycles. Prerequisites for process performance are surface preparation and optimized surface treatments, according to Steve Moffatt, CTO, Applied Materials. ALD growth rates vary with substrate type and condition — including morphology, contamination, and crystallography. De-gas and pre-clean treatments enable uniform, constant, linear film growth.
ASML's CTO S.I. Lee adds that, although ALD provides superior WIW uniformity, the process must be closely controlled to get satisfactory WTW and batch-to-batch (BTB) uniformities. "Further, the undesired gas phase mixing of ALD components must be avoided to prevent nonuniform film compositions across the wafer," explains Lee. "In addition, suppliers must provide a repeatable delivery method for precursor materials." Other considerations are shelf life and stability of the starting materials.
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Good high-k capacitors can be made with ALD, but performance issues still exist for the use of high-k dielectrics in transistors, according to Henk de Waard, business unit manager for transistor and capacitor products, ASM International (ASM). In particular, he cites threshold voltage shift and mobility of charge carriers (that negatively impact drive current) as active areas of research.
The major issue for ALD from a cost standpoint, however, is throughput; one estimate is that it deposits about 1Å/min. While smaller companies tackle this COO issue (see "Upstarts try multiwafer ALD for better throughput" on p. 40), ASM is readying its announcement of an ALD tool that does batch processing. "We want to offer both single-wafer and batch processing," states Willem Vermeulen, director of central marketing at ASM. The batch tool is targeted to the applications that require thicker layers and fits the company's overall strategy of offering both single-wafer and batch solutions across all product lines, whenever possible.
Applied Materials maintains that ALD is not as slow and expensive as people think, now that extremely small chambers and better gas delivery systems to move the gas in and out of the chamber faster have gotten cycle times down to <3 sec/cycle. "The perception is that this is just something academic, but we're able to demo a chamber that can run at 30wph, so we're hoping that will translate into earlier introductions," says Dana Tribula, director of marketing for copper, PVD, and integrated systems at Applied.
Who is doing what
IBM's principal interest in ALD is for the diffusion barriers that form the interface between copper and the dielectric layers in an interconnect structure and that prevent contamination of the copper. "IBM uses a two-layer system," explains Steve Rossnagel, research staff member at IBM's Watson Research Center. "The TaN sticks well to the dielectric, Ta sticks well to TaN, and Cu sticks well to the Ta."
Bob Gasser, director of the Components Research Group at Intel, reports that the company is especially interested in evaluating ALD for gate oxide deposition where thickness control is desired. "Our experience is that the nature of ALD does not change significantly based on feature size or technology use. So much of the learning from any previous applications of ALD should be cumulative."
Genus is expecting to capitalize on its cumulative experience with ALD in gap dielectrics for thin film heads (TFH). The company was out of the gate with ALD capability in 1999 and commercialized its gap dielectric application for TFHs in 2001. Genus says its tools for dielectrics are now being used in volume production of TFHs and it is getting repeat orders. The company expects its success to carry over into trench capacitors for DRAMs, which had been targeted by the end of 2002. The next target is gate dielectrics for logic applications in 2003.
Werner Rust, VP of sales and marketing at Genus, is particularly confident in the company's experience in the data storage industry. "The thin film head customers are more aggressive than IC manufacturers," states Rust. "TFH customers accepted ALD right away. We are getting valuable experience for improving tools and skills, as well as acting as a test bed before going to IC manufacturers."
Applied Materials says users of its tungsten ALD tool are starting to move from basic R&D into pilot production. They are primarily makers of embedded DRAMs challenged with filling high-aspect-ratio contacts without voids at 90nm. "But we're also seeing interest from core logic starting around 65nm," says Jerry Gelatos, director of Applied's Contact Metallization Division. He notes that interest in an extendible process that can survive multiple generations may push chipmakers to earlier adoption. Applied's TiN ALD for DRAM capacitor electrodes "is moving into production as we speak," adds Gelatos. He notes it qualified at the previous generation and will ramp at 90nm.
ASM's major push has been in FEOL ALD; the company considers itself a pioneer, having acquired Microchemistry of Finland in 1999, characterized by ASM as the inventor of ALCVD (although Genus announced its ALD capability in 1999 as well). According to de Waard, the company's cluster toolset is being geared up for high-volume manufacturing for transistor and capacitor applications at multiple sites — nine or 10 of the top 15 major IC manufacturers.
ASM has added plasma-enhanced ALD capability through its technology and marketing agreement with Genitech, a private Korean firm founded by researchers from the Korean government research institute Electronics and Telecommunications Research Institute, which worked on developing its tool with Hynix. The tool is not only set up to do ALCVD for FEOL capacitor applications, but de Waard notes that, for transistor applications, a complete integrated process solution is provided.
ASML is making its first major move outside its traditional lithography space in targeting the ALD market through a technology and marketing agreement with IPS, a $7 million Korean toolmaker that worked with Samsung to develop its tool. What's more, ASML has Samsung's former CTO, S.I. Lee, who oversaw much of Samsung's ALD development, now working in Scotts Valley, CA, as CTO of ASML's Thermal Division.
Jeffrey Kowalski, president of the Thermal Division, says ASML intends to be a fast follower in the capacitor market. While ALD now looks like it will be used for capacitors at 90nm, there are only two fab lines currently investing in 90nm tools, and orders may be pushed out 4–6 months. Fabs are actively evaluating the tools for purchase this year, however. The company has shipped a 300mm tool to a major DRAM maker for stack capacitor applications.
An evolving controversy
Wilbert van den Hoek, CTO and executive VP of Novellus, makes a distinction when describing ALD. "It's not really the deposition of a monolayer of film at a time; rather, it's the deposition of a fraction of a monolayer at a time," explains van den Hoek. He notes that in ALD, a monolayer of chemical A is absorbed on the surface. A second chemical B subsequently reacts with the absorbed monolayer to form a fraction of a monolayer of the desired material C on the surface.
Novellus has developed a technique it calls pulsed deposition layer (PDL). It uses sequential pulses of reactants with purge cycles between the reactant at elevated pressures. "A purist would say that PDL isn't truly ALD," notes van den Hoek. "We consider it to be a derivative of ALD. It is fundamentally an ALD process, but it operates at 2–10¥ the rate of a pure ALD process [see figure], and gets around the fundamental weakness of a feed-rate-limited CVD process — poor step coverage."
Similarly, van den Hoek believes that IPVD can be extended for barrier seed technology to the 65nm node. "At the 45nm node, we see movement away from IPVD nitrogen-doped Ta to either TiN or TaN using PDL," states van den Hoek.
What is next?
According to IBM's Rossnagel, the next frontier in ALD processing includes both Ta ALD and Cu ALD. IBM's interconnect technology needs both Ta and TaN for the foreseeable future, Rossnagel asserts. But equipment suppliers have not shown much interest in addressing Ta ALD. Why they have not is a matter for speculation.
"It's partly plasma and partly chemistry," states Rossnagel. "I find it surprising that suppliers are reluctant to use a plasma process since they are everywhere. However, the thermal-only ALD TaN process using a metal-organic Ta precursor is much easier, cheaper, and more reliable. It does not, however, solve the major problem of an all-ALD liner-seed environment."
Rossnagel is concerned that ALD TaN only solves part of the problem. "The ALD TaN should be able to replace the PVD TaN, but we still have to buy PVD Ta systems and continue to deal with the problems of uniformity, directionality, and redeposition for conformality." Rossnagel further notes that one of the only ways to get ALD Ta is to use a halogen-based chemistry, which, he says, works much better with plasma enhancement. IBM has been doing Ta ALD in its labs for the past three years.
Rossnagel explains that the bilayer structure is used by IBM for several reasons. "The TaN is deposited first, directly onto the dielectric." The TaN has two roles: 1) adhesion — Ta and/or Cu do not adhere very well to most dielectrics; and 2) acting as a diffusion barrier. IBM then deposits a layer of Ta on top of the TaN.
"This gives better adhesion for the Cu than Cu on TaN," comments Rossnagel. "If Cu is deposited directly on TaN, the electromigration resistance is poor. The Ta layer is not really a diffusion barrier for the Cu or dielectric contamination. It's a barrier of sorts, but not as good as the TaN."
Applied Materials' ALD technology program manager, Nirmalya Maity, does not believe that Ta ALD offers an advantage as a diffusion barrier over TaN. "For an ultra-thin barrier with good diffusion properties, amorphous ALD TaN is preferable to polycrystalline ALD Ta," explains Maity. "A bilayer of ALD TaN/Ta would be preferable and there may be other ways of achieving that than directly depositing ALD Ta."
Another objection according to Maity is that direct deposition of ALD Ta would involve the use of halogenated precursors with high deposition temperatures (>300°C). "This is not desired in Cu interconnect schemes due to the chance of residual halogen contamination at the Ta/Cu interface," states Maity.
IBM's Rossnagel, however, believes that the presence of halogen impurities is a process-related issue. "If the process is done well, the residual halogen levels can be virtually undetectable," explains Rossnagel.
 Step coverage vs. deposition rate in high-aspect-ratio structures (AR ~ 5, width ~ 100nm). Source: Novellus |
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Regarding Cu ALD, Maity thinks the concept of a thin (100–200Å) ALD/CVD Cu seed may be problematic for electrochemical plating on 300mm wafers. The field coverage would be too thin, particularly after some is etched away by the acid bath. "Making the seed layer any thicker would close up the via opening," explains Maity. "Further, thin Cu seed tends to agglomerate on most barriers at temperatures required for ALD or CVD processes (~300°C), so a more ideal seed profile would be to have 500Å on the field, 100Å on the sidewall, zero overhang, and low-temperature deposition — much more achievable using an advanced PVD technique." Another major issue is that no ALD or CVD Cu precursor has been identified that yields a film with acceptable adhesion to current barriers.
ASM is in the R&D phase with respect to ALD for BEOL applications, and expects to have a third-generation copper barrier/seed solution, targeting the 65nm node, for high-volume manufacturing in 2004. ASM is working with several consortia, universities, and other technology partners to make this happen, including NuTool Technologies' ECMD Cu process.
Genus' Rust has another way of describing how ALD will move into the market. "Furnaces (furnace oxidation) will feel it first, then CVD, including W CVD, and last, PVD (barriers for dual damascene)," explains Rust. He is especially excited about the 300mm tool that Genus shipped to Selete for high-k gate stack ALD applications.
Ken Monnig, International Sematech's associate director of interconnect, states that it will be difficult to see how the industry will get control of deposition and film thicknesses for barriers, seed layers, and damascene-type structures using conventional PVD and CVD. "ALD probably won't be used at the 90nm node — a lot of 90nm decisions are already made," comments Monnig. "But ALD-type solutions will have to be made at the 45nm node or less."
Monnig further cautions that it is not clear that there is anything about ALD that is better for porous low-k applications than CVD and hints that it might even be worse than CVD. "Even if ALD is OK for dense, low-k materials, it is not a slam dunk," states Monnig. "Additional work will need to be done to handle the pore sealing."
Debra Vogler, Senior Technical Editor, and Paula Doe, Contributing Editor, Solid State Technology
The market outlook by Paula Doe, Contributing Editor
While the $1 billion ALD market may still be out five years in the 65nm future, a crowd of players is targeting a market that is approaching $100 million now, with a boost of investment in the technology from Korea.
In the down year of 2002, the still tiny ALD market was at least one of the few growth sectors in equipment. Dataquest expects 40–50% growth, from $59 million in 2001 to some $80–90 million in 2002 as R&D labs buy a couple of tools each for their 65nm development work, and a few use the tools in production, mostly for memory capacitors. VLSI Research says it stands by its earlier projections for growth to some $60 million in 2002, from $33 million in 2001. VLSI figures about half the market is for capacitor applications, the other half divided among thin film heads, gate stacks, and interconnect barriers. ASM reported ALD tool sales of about $20 million last year; Genus reported $21 million. Dataquest figures Applied Materials also sold about $15–20 million worth of ALD tools.
But the big potential market is metal. "It really won't be an explosive market until metal barriers start to use it at 65nm and below," says Gartner Dataquest principal analyst Dean Freeman. He projects a $593 million market in 2007 for semiconductor tools, and another $300 million for thin film heads. VLSI Research's Risto Puhakka, VP of operations, concurs, "If ALD plays out inbarrier/seed, it will be a large market, with 7–8 layers/wafer anda half dozen systems per line. It looks very promising." VLSI projects a $1 billion total ALD market by 2006, including both semiconductor and data storage. Companies that can offer integrated technology look to have the edge. "Companies like Applied, Novellus, and TEL will have a big advantage, where users don't have to switch tools between the barrier and seed layers, which may still be PVD," says Freeman.
Back in the current market, a crowd of other players is scrambling to sell ALD tools for high-k dielectric films for DRAM capacitors now, logic gates to come, and a smattering of other niches. "Everybody and his aunt is getting into this market," says Puhakka. In what has to be an industry first, Korean technology is a driving force, thanks to major investment by both Samsung and the Korean government.
 Atomic layer deposition a) roadmap and b) market forecast. |
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Upstarts try multiwafer ALD for better throughput by Paula Doe, Contributing Editor
In the latest round of the ongoing scramble to improve ALD throughput, Torrex and Jusung are each touting multiwafer ALD systems.
Torrex says a user asked it to convert its multiwafer LP CVD platform for ALD, so it changed the gas delivery system to do the ALD load, hold, and purge pattern. The company's parallel cluster platform is rather like a single-wafer tool stretched vertically into 25 single-wafer tools, with gas shower heads on the side that distribute gas across all 25 rotating wafers at once. The company says it can do a 300Å film at 15 wafers/hr, or 5–10Å/min.
Torrex president and CEO Julio Guardado explains that the tool keeps the stack of susceptors at operating temperature all the time, and each wafer sits between two susceptors so it heats almost immediately, unlike a furnace that relies on wafers for its thermal load.
Torrex targets the thicker films for frontend applications, particularly SiN, Al2O3, and SiO2, where faster deposition is more of an advantage. The company announced delivery of its first tool in July for R&D, and Guardado says it is now negotiating repeat orders. He expects some users to roll out volume production in 2H03 or 2004.
"We see our main competition as the batch furnace companies," says Guardado. "Most of our films are 400–500Å." The company closed on an additional $15.5 million in financing from multiple venture capitalists in mid-October, bringing its total funding to some $38 million.
Besides its more conventional single-wafer ALD tool, Jusung, Gwangju, Korea, also has a multiwafer model, with four wafers/chamber and two chambers/platform, for 2–3¥ greater throughput than a single-wafer tool. The gases are delivered through different arms of a cross, which rotates over four wafers laid out horizontally in one chamber, sequentially exposing them to source, purge, reactant, and purge gases. The tool is aimed at applications such as TiN for metal electrodes, where integration with other processes is not required.
Jusung VP of sales, marketing, and investor relations Joachim Nell argues recent improvements in throughput mean ALD will be adopted sooner than most people think. "ALD will clearly be used at 90nm. There's a strong need in embedded DRAMs and DRAMs, and in going from polysilicon to metal electrodes," says Nell. "I'm very sure that if people see the high throughput it will be adopted very fast."
Jusung's single-wafer tool, which can handle up to four chambers/system, is aimed at applications that benefit from integration with other ALD or CVD chambers for things like composite high-k dielectrics.
The company says it has fully qualified Al2O3 and TiN, and is in the process of final qualification of HfO2. Customers are using the tools in small volume, pilot production.