Accurate measurements in the DUV PEB process
01/01/2003
overview
The 2001 International Technology Roadmap for Semiconductors (ITRS) shows the microprocessor gate 3s criticaldimension control shrinking from 4.3nm in 2002 to 2.0nm in 2007 [1]. Maintaining such critical dimension requirements means that controlling temperature in the post-exposure bake step is crucial.
The chemically amplified resists employed at the 130–70nm technology nodes require post-exposure bake (PEB) steps where the photo-acid catalyst generated by the exposure renders the resist soluble in a developer solution.
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The PEB sensitivity of deep ultraviolet (DUV) resists to temperature, however, is forecast to decrease from 3nm/°C in 2002 to 1.5nm/°C in 2007.
The PEB process consists of four thermal steps: The wafer is transferred from a chill plate to a hot plate; the wafer remains at a steady-state temperature,typically 90–140°C, for 1–2 min; the wafer is transferred from the hot plate to the chill plate;and the wafer is cooled on the chill plate.
 Figure 1. Temperature range in the isothermal bath vs. number of cycles. The bath temperature is 100°C. |
Each step makes a contribution to the thermal dose received by the photoresist. The critical dimension (CD) variations across the wafer depend on local variations of rise times, steady-state bake temperatures, times at bake temperature, and cooling times to the chill plate temperature.
During the thermal-processing steps, three reactions compete in the exposed resist. In one reaction, the photo-acid catalyst is lost to the environment. In a second, the photo-acid developer diffuses through the resist. In the third reaction, the photo-acid deprotects the resist, thus rendering the resist soluble in a developer. Some resists, such as APEX-E, have diffusion and deprotection activation energies around 36kcal/mol. The activation energy of the acid loss reaction is around 5kcal/mol.
A model of APEX-E is provided in PROLITH version 7.0 for characterizing the resist CD sensitivity to thermal treatment [2]. This is a 248nm resist with a lower-temperature bake than the 193nm resists. During the ramp to steady-state temperature, the acid loss mechanism starts at low temperature — before the deprotecting mechanism with a higher activation energy is activated. As a result, the resist CDs of dense lines increase 50–100% for rise time constants greater than 7 sec.
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Accurate knowledge of the ramp temperature profile is therefore necessary to ensure dimensional control. The cooling process is less critical because the high activation energy for deprotecting quenches the reaction quickly as the wafer cools. Also, isolated lines are less sensitive than dense lines to ramp time variations.
Direct measurement of the wafer in the PEB system is a reliable way to acquire thermal information about the temperature profile. Knowledge of the temperature profile can then be used to reduce the contributions to the CD variation.
Sensor instrumentation
Small thin-film resistance temperature detector (RTD) sensors packaged in ceramic are placed into cavities machined into the wafer. The sensor resistance is nominally 1000W at 0°C with a temperature coefficient ofresistance (TCR) value of 0.00375W/W/°C. The sensor dimensions are 1.52 ¥ 0.76 ¥ 0.31mm. The thermal properties of the protective coating closely match those of silicon and the thermal response time constant of the silicon wafer is practically unperturbed by the incorporation of the sensors. Further, all regions of the wafer behave with a thermal response similar to a product silicon wafer. In this study, 17 sensors are embedded into 200mm wafers and 29 sensors are embedded into 300mm wafers.
Temperature tests
Three types of tests were performed with the instrumented wafers: in an isothermal bath, on a uniform temperature hot plate, and on a PEB hot plate. In the isothermal bath test, the 200mm wafers are measured before and after thermal cycling on a PEB hot plate. Performing this isothermal test provides information about the drift of the sensor elements due to thermal cycling. During the test, the wafers are held at the calibration temperatures for five minutes while the pyrometer (PRT) reads a constant temperature. Temperatures are acquired every 2 sec. Three 200mm wafers are tested; their numbers are 47416, 47428 and 47429.
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In the hot plate test, the 200mm wafers are placed on a uniform temperature hot plate for monitoring in a steep vertical thermal gradient. The high thermal mass copper hot plate is designed to minimize thermal gradients across the wafer, and hot plate temperature is controlled to 140°C. A wafer rotation test checks the repeatability and reproducibility of the sensor measurements. Further, the rotation test is capable of determining nonuniformities on the wafer and the hot plate. The temperature acquisition interval is 1 sec. The rotation tests on the uniform hot plate are performed before and after thermal cycling on a PEB hot plate to determine the drift due to thermal cycling. The temperature cycles are 90 sec at 250°C.
 Figure 2. Temperature offsets vs. bath temperature for wafer 47428. |
In the last test, the 300mm wafers are heated on a production PEB hot plate and cooled on a chill plate. This test studies the dynamic as well as the steady state wafer temperature during the PEB process. The temperature uniformity of the multizone hot plate is initially optimized using the instrumented wafer. The wafers are transferred robotically to and from the PEB plate. Rise time and cool time studies are performed when the plate is heated to 140°C. Because of the rapid thermal changes, the temperature measurement interval is set to 0.5 sec.
Isothermal bath tests
The temperature ranges for the isothermal bath tests are listed in Table 1. The temperature range is the difference between the maximum and minimum temperatures of all the sensors on the same wafer when the wafer is exposed to a certain thermal environment. Ideally, the temperature range at the calibration points is 0°C.
The temperature ranges immediately after calibration may not be 0°C, due to errors of the measurement tools, hysteresis associated with the sensors, and uncertainties of the curve fit coefficients in the calibration curves. In fact, at 100°C immediately after calibration, the range is 0.012–0.017°C.
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The ranges on all wafers show some increase after the cycling tests. After 500 or more cycles, the ranges vary from 0.033 to about 0.100°C, depending on the number of cycles and the measurement temperature. At high temperature, the range of wafer 47416 increases about 0.050°C more than the range of wafer 47428. The cause of the difference is not clear. Not all wafers are subjected to the same number of PEB cycles at each of the test points. The trend illustrated in Fig. 1 suggests that most of the increase to the range might occur in the first 100 cycles. Further tests are needed to confirm this hypothesis.
 Figure 3. Sensor temperatures during rise to PEB temperature. |
The offsets between the mean wafer temperatures and the PRT temperatures are listed in Table 2. The deviations are computed by subtracting the PRT temperatures from the mean temperatures measured by all the RTDs on the wafer. Before the PEB cycling, the deviations at 100°C range from -0.016 to -0.023°C. For wafers 47416 and 47429, only small changes occur to the 100°C deviation when thermal cycling takes place. As the number of cycles increases, the offsets at 100°C remain negative and stay within 0.014°C of the offsets at 0 cycles. The offsets at temperatures lower than 100°C become more positive than the 100°C offset. The offsets at higher temperatures tend to become more negative as the cycling increases.
The temperature offset trend for wafer 47428 is illustrated in Fig. 2. As the number of thermal cycles increases, the slope of the deviations becomes more negative. By 2000 thermal cycles, a noticeable slope develops. Further, all 17 sensors exhibit the trend shown by the mean in Fig. 1. This analysis is based on one wafer (17 sensors) and two sets of cycling test data. If the test is repeatable, the drift of the RTD calibrations over the thermal cycle to 250°C is demonstrated.
Uniform hot plate tests
Since the temperature on the hot plate is not perfectly uniform, a rotation test on the hot plate allows the temperature precision of the sensors on the wafer to be determined. The temperature ranges of the 17 sensors are monitored so that the measurements are obtained every 90° of rotation — the wafer is rotated clockwise through 360° and then rotated counterclockwise so temperatures at each orientation are measured twice. The mean ranges at each stage of the cycle testing are listed in Table 3; also listed are the ranges of the means.
 Figure 4. Temperatures during transfer to the chill plate. |
Before thermal cycling, mean ranges are 0.035–0.040°C. The ranges on the hot plate, therefore, are 0.020°C higher than the ranges obtained in the isothermal bath. The increase to the range is due to two sources. First, the temperature across the hot plate is not as uniform as the temperature in the isothermal bath. Second, the sensors are heated in a vertical temperature gradient. Variations in thermal coupling of the sensors to the wafer may cause temperature measurement variations. Both effects combine to increase the range by 0.020°C.
As the number of thermal cycles increases, the mean range increases. The trend on wafer 47428 shows that the range can stay below 0.060°C even after 2000 cycles. On wafer 47428, the range increases monotonically as the number of cycles increases. This increase may be due to slow degradation of the bond between the sensor and wafer or drift of the RTD resistance.
For temperatures between 100 and 140°C, the ranges in the isothermal bath and on the hot plate are listed in Table 4, along with the differences between the hot plate and isothermal bath uniformities. The differences between the hot plate and isothermal bath ranges are about the 0.020°C amount attributable to the hot plate. Therefore, the variation in range observed in the cycling test is mostly due to degradation observable in the isothermal bath test — probably caused by the drift of the resistance of the RTD and, to a lesser degree, by the degradation of the bonding of the RTD to the wafer.
PEB plate tests
The temperature traces obtained during the rise to bake temperature on a production PEB plate are shown in Fig. 3. The sampling interval is 0.5 sec. During the first 15 sec of the rise to bake temperature, the sensor temperatures exhibit a significant dispersion that is quantified by a nonlinear fit to a heat transfer model. The time constant for the rise to PEB plate temperature is extracted by a nonlinear fit to the temperature profile [3]. The fit is made to the equation,
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where trise is the rise time constant and to is an adjustment allowing for start time variations across the wafer and an uncertainty in the measurement of the start of the temperature rise. The nonlinear fit therefore determines two parameters. A trise and to are computed for each RTD. Histograms of trise and to indicate that the average trise is 5.20 sec. The standard deviation for trise is 0.11 sec. The trise ranges from 4.94 to 5.38 sec. The average to is 0.45 sec. Because the range of to is less than the 0.5 sec resolution of the data acquisition, further refinement should focus on shorter data acquisition intervals.
Figure 4 is a plot of the sensor temperatures during the transfer to the chill plate. Values of the time constant, ttransfer, which describes the cooling rate during the wafer transfer, are evaluated from an equation similar to Eqn. 1, with trise replaced by ttransfer.
During the transfer step, several sensors cool more rapidly than other sensors, so the variation of transfer time constants is greater than the variation of the rise time constants. Because of the short duration of the transfer step and the small temperature drop, ttransfer is not determined to the same precision as trise. The average standard error for ttransfer is 3 sec; the average ttransfer is 169 sec. The ttransfer values range is 81–219 sec and the standard deviation for ttransfer is 35 sec.
Figure 5 is a plot of the sensor temperatures as the wafer cools on the chill plate. The cooling rate on the chill plate is characterized by a chill time constant, tchill.
The time constants for the chill on the cool plate are comparable to the heating time constants. The average tchill is 5.04 sec. The tchill range is 3.31–5.99 sec, while the standard deviation for tchill is 0.54 sec.
The average time constants for the three dynamic PEB temperature steps are summarized in Table 5. The average rise time and average chill time constants are within 0.16 sec. Further, the rise time constants observed in the PEB chamber are below the 7 sec critical time cited in Ref. 2. Temperature uniformity is best during the heating process because the standard deviation for trise is lower than the standard deviations of the other two time constants.
The time constant is expressed as
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where r is the density of silicon, Cp is the heat capacity of silicon, L is the wafer thickness,kairis the thermal conductivity of air, d is the gap between the wafer and hot plate and h is the heat transfer coefficient for heat lost to the surroundings.
When the wafer is in close proximity to the hot plate, the term kair/d dominates h. The 5.20-sec value of trise is consistent with the 100µm gap, the wafer thickness, and the thermal properties of air. When the wafer is far from the hot plate, heat is lost to the environment and the denominator is determined by h. The 169-sec value of ttransfer corresponds to a heat transfer coefficient, htransfer, of 7.1Wm-2K-1. The coefficient of heat transfer between the wafer and the chill plate, hchill, determines tchill. The 5.04-sec tchill value corresponds to a hchill of 239Wm-2K-1.
Conclusion
A temperature monitoring system capable of measuring dynamic and steady state PEB temperatures with high accuracy — ensured by a NIST traceable calibration — and precision has been demonstrated. The temperature precision as measured on a uniform temperature hot plate is ±0.030°C. A heat transfer model accurately extracts time constants to describe the heating and cooling segments of the temperature profiles measured in a production PEB chamber.
 Figure 5. Sensor temperatures during the wafer cooling on the chill plate. |
Reliability studies show the temperature ranges and offsets drift somewhat over 2000 thermal cycles. Most of the drift probably occurs in the first 100 cycles. Further work will evaluate the effectiveness of the photoresist model to correlate CD variations with direct measurements of the PEB thermal cycle and the sources of range and offset drift.
References
- Semiconductor Industry Association, International Technology Roadmap for Semiconductors, 2001 edition, Austin, TX; International Sematech, 2001.
- M.D. Smith, C.A. Mack, J.S. Petersen, "Modeling the impact of thermal history during post-exposure bake on the lithographic performance of chemically amplified resists," Proc. SPIE, 4345, pp. 1013–1021, 2001.
- N. Ramanan, F.F. Liang, J.B. Sims, "Conjugate heat-transfer analysis of 300mm bake station," Proc. SPIE, 3678, pp. 1296–1306, 1999.
Acknowledgment
This article is based on a presentation given at the 8th International Temperature Symposium, sponsored by NIST, Chicago, IL, Oct. 21–24, 2002.
For more information, contact Mei Sun, SensArray Corp., 47451 Fremont Blvd., CA 94538; ph 510/360-5600, fax 510/360-5601, [email protected].