SPA plasma for sub-100nm
01/01/2003
overview
As semiconductor designs are downscaled to sub-100nm nodes, low thermal budgets and critical requirements for microscopic uniformities, such as low micro-roughness, along with process dependency on crystal orientation and materials, will all be more important. To address these issues, radical process changes will be needed.
Plasma characteristics of a slot plane antenna plasma reactor were investigated — especially the ability of its low electron temperature and high plasma density to achieve damage-free processes. Also, successful oxidation and nitridation using a slot plane antenna plasma were demonstrated for several applications such as the conformal corner oxidation for shallow trench isolation (STI), the recovery oxidation after poly/metal gate electrode etching, nitrided gate dielectric formation, and post-treatment of high-k gate dielectrics.
 Figure 1. a) Gate leakage reduction by SPA plasma nitrided gate oxide (PNO); and b) small degradation in Ion for an SPA PNO. |
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One of the most critical issues for manufacturing devices of 90nm node and beyond is gate dielectric formation with an equivalent oxide thickness (EOT) of ≤1.4nm. Conventionally grown thermal SiO2 has limitations in boron penetration immunity and direct tunneling leakage. Recently, plasma nitridation of the ultrathin silicon oxide (PNO) has been successfully adopted as a very promising gate dielectric to solve these issues. In particular, the microwave plasma generated by a radial line slot antenna (RLSA) was shown to be damage-free and able to form highly reliable dielectrics for advanced gate applications due to its low electron temperature characteristics [1, 2]. Through the optimization of the slot pattern and its configuration, this RLSA plasma technology has been improved and slot plane antenna (SPA) microwave plasma has shown very good scalability as wafer size is increased from 200mm to 300mm [3, 4].
Following the gate PNO application, SPA plasma has also proven its capability for processes such as flash tunneling oxide formation, conformal corner oxidation of shallow trench isolation, recovery oxidation after poly/metal gate electrode etching, post-treatment of high-k gate dielectrics, and nitridation of the poly-Si electrode prior to high-k film deposition for DRAM capacitors. The damage-free characteristics of SPA plasma and its performance in the above processes are introduced in this paper. The versatility of SPA plasma in critical processes indicates its potential for manufacturing devices at the 65nm node and beyond.
SPA plasma
Based on the RLSA microwave plasma developed by Prof. Tadahiro Ohmi at Tohoku University, microwave radiation at 2.45GHz is uniformly distributed about an antenna and propagates into the reactor through a top dielectric plate. As the skin depth of the microwave radiation is several millimeters or less, the plasma is activated within only a couple of centimeters from the top dielectric plate, and the electron temperature rapidly decreases with the distance from the plate. On the wafer, the electron temperature (Te) measured by a Langmuir probe was as low as 0.8eV at 130Pa in Ar plasma.
By optimizing the slot configuration of the antenna, the plasma distribution can be adjusted to achieve uniformity. The measured plasma density (Ne) was 5 ¥ 1011cm-3 with a nonuniformity of ±2% at 130Pa for the same plasma condition described above for both the 200mm and 300mm reactors; the similarity in Te and Ne for these reactors indicates the good process compatibility between them. The wafer temperature is controlled to a maximum of up to 500°C by the resistive heater in the wafer susceptor. At the increased temperature, the film quality was improved by eliminating the carbon and the water adsorbed on the wafer.
 Figure 2. Improvement in gate leakage reduction of HfSiO4 by SPA post-oxidation. |
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Advanced gate dielectric applications
The first SPA application considered is the plasma nitridation of PNOs. Figures 1a and b show the performance in the gate leakage (Ig) and the on-current (Ion) of an n-ch FET, respectively. Here, 8Å of the base oxide was formed by wet oxidation in a furnace using catalytic water vapor generation technology. An EOT of 9.5Å was achieved with the leakage reduced by 4¥. At the same time, no degradation in Ion was detected and the shift in the transistor threshold voltage (Vth) was <20mV. In a p-ch FET, Ion was improved due to the suppression of boron penetration from the p+ doped poly-Si to the channel. Here, no additional post-anneal is necessary after SPA nitridation, because the plasma damage induced by the process was negligible due to its low electron temperature. PNO technology using the damage-free SPA plasma is therefore expected to be a promising solution for gate dielectrics not only at 90nm, but also at the 65nm node.
For ultrathin base oxide formation in 65nm node devices, the in situ SPA plasma oxidation is the most likely technology candidate because the consecutive oxidation followed by nitridation can eliminate wafer contamination by ambient impurities such as organic materials and water. Using SPA plasma, 6Å of SiO2 was formed with a nonuniformity of ≤1%. This ultrathin oxide can be used as the interface layer for the high-k gate dielectric as well as the base oxide for PNO.
 Figure 3. Cross-section TEM of W/Poly-Si gate electrode after recovery oxidation by SPA plasma. |
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Other promising applications of SPA plasma are post-oxidation and post-nitridation of high-k films. Compared to post-thermal nitridation, the gate leakage of the HfSiO film was improved by SPA post-oxidation, and the EOT was slightly increased with SPA post-oxidation (Fig. 2). This improvement in the leakage can be attributed to the reduction of carbon incorporated into the high-k film. Thermal stability and the boron blocking performance of HfSiO were also improved with the SPA post-nitridation.
There are several possible applications of SPA plasma in DRAM gate processes. SPA plasma nitridation of the gate oxide in the peripheral circuit is the most likely application because the boron in the p+ poly-Si gate electrode is easily diffused into the channel due to the large thermal budget of DRAM capacitor formation. Also, low-temperature recovery oxidation after etching the poly/metal gate electrode by SPA plasma is expected because high-quality oxide can be formed on the substrate and the poly-Si without any recess of W due to WO3 evaporation (Fig. 3).
Flash applications
The tunneling oxide of flash memory devices is facing limitations with respect to reliability degradation around 10nm. A radical oxidation process was needed. SPA plasma oxidation was shown to provide reliable tunneling oxide at low temperatures (≤500°C) and showed no degradation in QBD (charge to break down, i.e., amount of charge at the defined breakdown percentage) when its thickness was reduced from 10.0nm to 8.0nm. The superiority of SPA plasma oxide was also observed after subsequent high-temperature densification. Similar superiority in stress-induced leakage current (SILC) performance was achieved vs. that achieved with thermally grown oxide. In addition to this tunneling oxide application, SPA plasma can be used for ONO film formation with the combination of oxidation and nitridation.
 Figure 4. Conformal oxidation by SPA plasma: a) whole view, b) top view, and c) bottom of the trench. |
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STI applications
Conformal thickness and rounded corners are critical for eliminating leakage at the active edge of junctions and the double hump in the Id-Vg curve. Low-temperature radical oxidation rate is independent of crystalline orientation and materials. Utilizing these process characteristics, SPA plasma can be used for STI corner oxidation. The SPA oxide was formed conformally at the STI corner, and the oxide thickness was almost the same at the top, side and bottom (Fig. 4). The radius of the STI top corner was equivalent to the oxide thickness, and the round shape was obtained without additional rounding processes.
 Figure 5. Improvement in oxidation immunity with SPA plasma nitride over a Si substrate. Refractive index = 1.462. |
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DRAM capacitor applications
One of the issues in DRAM capacitor formation is the increase in the effective thickness of high-k dielectrics caused by re-oxidation of the lower poly-Si electrode during high-temperature chemical vapor deposition and the following oxidation process. Nitridation using SPA plasma promotes oxidation immunity compared to conventional rapid thermal nitridation (RTN). The nitrided Si surface by SPA plasma showed excellent blocking performance against the following rapid thermal oxidation up to 850°C (Fig. 5). On a nitrided surface treated by RTN, oxidation took place gradually at >600°C. This strong oxidation immunity of SPA plasma nitride can be attributed to the smaller number of nitrogen defects in the film.
Due to the large activation energy necessary, thermal nitridation requires high temperature, ≥~1000°C, resulting in a large disturbance in the channel profiles. The issue becomes critical when the nitridation process is necessary in device manufacturing. At that point, SPA plasma nitridation provides the solution.
Conclusion
A microwave SPA plasma process results in electron temperatures <1.0eV. Because of its damage-free characteristics, SPA plasma has promise for critical process applications at the 65nm node and beyond. Examples include plasma-nitrided gate dielectrics, high-k gatedielectric formation, the recovery oxidation after poly/metal gate electrode etching, the conformal corner oxidation of STI, and poly-Si nitridation prior to high-k deposition for DRAM capacitors.
References
- K. Sekine, Y. Saito, M. Hirayama, T. Ohmi, VLSI Tech. Symp., p. 115, 1999.
- Y. Saito, et al., VLSI Tech. Symp., p. 176, 2000.
- T. Hongo, S. Suzuki, ASET Research Report on High Efficiency Semiconductor Manufacturing Process Tech., 2000.
- T. Nozawa, M. Inoue, S. Ozaki, S. Murakawa, to be published in ISSM, 2002.
Shigemi Murakawa is a product manager of Trias SPA for the Single Wafer Deposition business unit (BU) of Tokyo Electron Ltd., TBS Broadcast Center, 3-6 Akasaka 5-chome, Minato-ku, Tokyo 107-8481, Japan; ph 81/3-5561-7967, fax 81/3-5561-7396, [email protected].
Takenao Nemoto is in charge of business development for the Single Wafer Deposition BU of Tokyo Electron Ltd.
Yoji Iizuka is in charge of business development for the Single Wafer Deposition BU of Tokyo Electron Ltd.
Nobuhiko Yamamoto is a project manager at Kansai Technology Center of Tokyo Electron Ltd.
Shigenori Ozaki is a chief project engineer at the Kansai Technology Center of Tokyo Electron Ltd.