Technology News
12/01/2000
A view into Selete's 300mm program
The on-going evaluation, since July 1999, of FSI International's ZETA 300mm surface conditioning system gives a good view into Japan's Selete 300mm tool selection program and the rigors of 300mm processing specifications in general.
The ZETA system is capable of relevant standard chemistries including rinsing and drying (RD), ammonium-hydroxide hydrogen-peroxide mixture (APM or SC1), sulfuric-acid hydrogen-peroxide mixture (SPM or piranha), hydrochloric-acid hydrogen-peroxide mixture (HPM or SC2), and dilute hydrofluoric acid (DHF).
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For wet cleaning equipment, Selete's initial characterization looked at particle and metal neutrality, and etch uniformity for the standard process sequences on bare silicon wafers or thermal oxide wafers. FSI's Scott Becker tells Solid State Technology, "Selete's particle test specified <30 0.17µm-particles/wafer and evaluated SPM-DHF-APM-HPM, APM only, and SPM only recipes (see table).
Becker continues, SELETE's metallic contamination specification required the concentration of critical elements to be <1x1010atoms/cm2 for SPM-APM-DHF and SPM-DHF-APM-HPM recipes.
Test results by TXRF showed that our system's metallic contamination was <109 atoms/cm2 for SPM-DHF-APM-HPM and <1x1010 atoms/cm2 for SPM-APM-DHF on bare silicon wafers."
In other tests, Selete engineers evaluated etch uniformity on the DHF recipe, with an etch target of ~10nm and nonuniformity within ±5% 3s using a 13 point test for on-wafer, wafer-to-wafer, and lot-to-lot tests. The ZETA system achieved 1.20-2.55% nonuniformity on all the tests.
Selete's process characterization also evaluated particle and metallic contamination removal. Becker says, "The APM-R/D process was able to reduce a challenge of 1000-4000 silicon particles (>120nm) by over 90% on bare silicon wafers and also was able to reduce a challenge of 10,000-20,000 silicon particles by over 95% on oxidized silicon wafers. In addition, metallic contamination challenges of Al, Fe, and Cu were reduced by over 99% on the wafer surface by standard process sequences."
Selete engineers also focused on process applications, specifically resist strip and post-salicide (Ti and Co) formation etch. Becker says, "They found that a standard photoresist strip and cleaning sequence of SPM-APM-R/D performed well, adding <10 particles (>120nm) to a 300mm wafer on average. Further, the system stripped 3µm of i-line photoresist or 0.85µm of KrF photoresist without adding particles. TXRF measurements indicated that metallic contamination was <109 atoms/cm2." Details on post-salicide formation etch performance are still pending.
Selete characterizes 300mm equipment reliability during two marathon periods in which a standard process sequence is looped continuously over an extended period to simulate wafer production. Each marathon cycle includes unloading wafers from a FOUP, loading them into the process chamber, running the designated process, unloading wafers from the chamber, and returning them to the FOUP. For the FSI system, the first marathon was a three-day, 200-run "cold marathon" (i.e., a DI water rinse and dry). The second, was a two-day, 40-run "hot marathon" (i.e., SPM-HF-APM). Along with process performance in both, safety and mechanical handling characteristics were evaluated during the marathons.
Becker says, "Selete's particle acceptance condition for the cold marathon was <10 particles at >120nm measured on three wafers/100-wafer batch."
Hot marathon results will be released by Selete for public disclosure in February 2001.
Since April 2000, Selete has been evaluating 130nm process technology in its three-year Phase II evaluation; only systems that successfully completed Selete's Phase I evaluation were invited to participate in Phase II. Its engineers consider that five modules are key: shallow trench isolation and poly-metal gate stack, self-align contact etch and filling, high aspect contact-via etch and filling, via etch and filling, and copper damascene. In these modules, the wet clean step performs the critical function of pre-process surface preparation and post-process residual removal. Selete is evaluating four wet clean systems.
Becker says, "Our ZETA system will be evaluated for photoresist stripping using SPM-based and, later, DIO3-based chemistries. The ZETA system will also be evaluated for titanium and cobalt strip post-salicide formation, Cu and low-k cleaning, post-Cu CMP cleaning, poly metal gate cleaning, and post-RIE residue removal. New aqueous solvents will be explored." — P.B.
Low-energy plasma-enhanced CVD facilitates high mobility SiGe
A record hole mobility for a MOSFET has been achieved with a low-energy plasma-enhanced CVD process developed by Unaxis Semiconductors, Balzers, Liechtenstein, and ETH Zurich, the Swiss Federal Institute of Technology.
 MOSFET with strained Ge-rich channel grown by low-energy plasma-enhanced CVD. (Source: Unaxis.) |
Ge has the highest hole mobility of any semiconductor (1900cm2/Vsec), so Ge-rich layers of Si1-xGex have hole mobilities much higher than that of Si (200cm2/Vsec). These layers are therefore of much interest as the channel in enhanced p-type MOSFETs. However, strained Si1-xGex can be grown in an appropriately thin layer on Si only if the Ge fraction x is fairly low, resulting in a low hole mobility in the channel. The new process reported here addresses this problem by creating a strain relieved buffer layer composed of Si0.52Ge0.48. This allows the 12.5nm thick Si0.17Ge0.83 channel shown in the figure. The hole mobility measured 760cm2/Vsec at 300K, which approaches the electron mobility of conventional Si NMOS transistors.
These structures were created with a low-energy plasma-enhanced CVD process. A key advantage of this process is the ability to vary the epitaxial growth rates over a wide range (0.08-5nm/sec). The buffer layer has a graded composition (with a final Ge fraction of 48%), and this was grown at 5nm/sec while varying the relative amounts of SiH4 and GeH4 to create the varying composition. This high growth rate is needed for the fabrication of the required thick buffer (6.5µm in this case) in a reasonable processing time. After this buffer layer was created, the temperature was lowered to 500°C and other conditions were changed to make the plasma density near the substrate much lower, resulting in a 0.08nm/sec growth of the Ge-rich channel. The very low growth rate in the channel layer is needed to suppress the segregation of Ge, and to be able to control the channel layer thickness. The low processing temperature also increases the options for film deposition on previously processed wafers.
Collaborators on this work were Daimler Chrysler Research and Technology, Ulm, Germany, and the Department of Electron Devices and Circuits at the University of Ulm. — J.D.
IBM's SOI nears 0.13µm process qual, new gate insulators needed
IBM's silicon-on-insulator technology program, which qualified a 0.18µm manufacturing process over the summer, is close to qualifying a 0.13µm process that will enable production of high-performance devices with 44 million transistors and effective channel lengths of just 0.08µm. But continued evolution of SOI beyond the 0.1µm level may be stymied by the need for new gate insulator materials.
Speaking at the IEEE Electron Devices Society International SOI Conference in Wakefield, MA, Fari Assaderaghi of IBM's Hopewell Junction, NY, Semiconductor R&D Center said the computer giant had begun shipping AS400 servers with 0.22µm SOI devices earlier this year, and that the newly announced "Turbo" Unix machines would use 0.18µm SOI processors running at "well above 800MHz."
The 0.18µm designs utilize shallow trench isolation, dual work function poly local interconnect, and borderless tungsten interlayer interconnect.
The successor 0.13µm process, which is "near complete qualification," will allow for a 128mm2 die, seven layers of copper metallization, and a gate oxide thickness of just 22Å. Assaderaghi noted that IBM is using both bonded and SIMOX SOI wafers, and is evaluating both for manufacturing. In addition to enabling reduced supply voltage and lower power density, the SOI devices bring performance boosts of 15-40%, depending on the type of circuit element.
Assaderaghi noted that gate oxides would need to thin to 10Å for the planned 0.1µm generation, and to just 6Å for a 0.07µm (70nm) generation. "At 70nm, a lot of previous assumptions break down," he said. "It looks very, very different in terms of generic technology, and there are many problems we have to resolve..." Development of a suitable high-k gate insulator is a must; Assaderaghi cautioned, "it is yet to be seen if we can overcome this fundamental barrier."
Design models for SOI are a challenge for many producers; IBM uses SPICE-like models developed in conjunction with the Univ. of California-Berkeley, based on its BSIM-SOI simulator. Another conference speaker, Christophe Tretz of Advanced Micro Devices' California Microprocessor Division, noted that SOI designers will need a greater awareness of device physics than they do with traditional CMOS, particularly floating body effects and reduced junction capacitance. Use of the high-speed "Domino logic" design can play into SOI's strengths, he said, while analog portions of SOI circuits (such as PLLs, VCOs, and SRAM cells) need significant redesigns from their CMOS counterparts. — P.D.
New elastic probe for MOS testing of production wafers
Solid State Measurements, Pittsburgh, PA, has introduced a novel probing technology that allows for testing of MOS structures in the scribe lines of production wafers. The key to the approach is an elastic probe tip made with a proprietary metal structure that deforms elastically to make contact on an exposed oxide surface. With silicon underneath, this makes a MOS structure that allows more characterization of gate dielectrics on the wafers than other probing techniques.
A nondestructive probe tip allows production wafers to be used. Since the tip makes good contact by deforming elastically against the surface when it is pressed down, it does not need to travel in the plane of the wafer for scrubbing to make contact. The motion of the probe is therefore constrained to the z-dimension only. The resulting placement accuracy and the 30µm probe tip diameter allow its use in scribe lines, without taking up wafer real estate.
The first product to be introduced with the technology is the SSM610 Gate Dielectric Quality Control System. It is designed for sub-5nm SiO2 and high-k gate dielectrics, and can measure equivalent oxide thickness, physical thickness, interface trap density, stress-induced leakage current, contaminant levels, and dopant density in diffused and implanted layers. The line of equipment can perform electrical inspection of production wafers at 60wph. For comparison, corona MOS biasing, in which a corona charge placed on the surface of the wafer creates the MOS structure, has a throughput of 5-10wph, with a much larger test area forcing the use of monitor wafers. A mercury probe CV system has a throughput comparable to the elastic probe system, but monitor wafers are needed because of the size of the mercury probe. —J.D.
Preventing microbubbles in filtration
Reduction of microbubbles in spun-on thin-film coatings, including developers, photoresists, solvents, and antireflective coatings, is becoming increasingly important in wafer processing. Consider, for example, positive resist developers, which are typically dilute tetramethyl ammonium hydroxide (TMAH) solutions. Trends to smaller feature sizes and larger diameter wafers necessitate the addition of surfactants to TMAH to ensure complete wetting of the wafer surface. However, use of filtration with developer dispense raises concern if the surfactant is stripped when adsorbing to the filter material. Generation of microbubbles is an additional concern, exacerbated by the presence of surfactants.
To add to the knowledge in this increasingly crucial area, a group of engineers at Pall have determined that the native high critical wetting surface tension (CWST) of Nylon 6,6 filters helps control microbubbles in developer and solvent applications.
This work, reported at the recent Arch Chemicals Interface 2000 conference, is the collaborative effort of Shuichi Tsuzuki at Nihon Pall Ltd., Ibaraki, Japan, and Barry Gotlinsky, Joseph O'Sullivan, Munaf Tinwala, and Michael Mesawich at Pall Corp., East Hills, NY.
 The accumulated count of >0.1µm microbubbles downstream from filters. (Source: Pall Corp.) |
At Interface, Tsuzuki told Solid State Technology, "The high CWST of Nylon 6,6 allows for spontaneous wetting of the filter medium without adsorbing surfactant. In addition, high CWST membranes do not trap any microbubbles; this indicates that microbubbles do not adhere to Nylon 6,6. We believe that the hydrophilicity of the Nylon 6,6 filter aids in reducing microbubbles and start up time in dispense applications."
The tests behind this conclusion used filter membranes constructed of PTFE (polytetrafluoroethylene), HDPE (high-density polyethylene), PES (polyethersulfone) and Nylon 6,6; PTFE and HDPE are hydrophobic, PES and Nylon 6,6 hydrophilic and wettable with TMAH. In all cases, the removal of particles occurs throughout the depth of the membrane.
A gallon of TMAH solution was circulated through each filter at a constant flow rate. Downstream microbubble (see figure) counts were monitored continuously with a laser particle counter. In addition, the surface tensions of the TMAH solution passed through the filters were measured to determine any change.
Tsuzuki said, "Our result indicates that Nylon 6,6 and PES filters are suited for use with surfactant-containing developer solutions; both will spontaneously wet with TMAH-based developer solutions, which can be attributed to high CWST (77mN/m and 72mN/m, respectively). In contrast, the HDPE and PTFE filters will not wet with TMAH due to the lower CWST (34mN/m and 31mN/m, respectively).
"In addition, we noted an increase in developer surface tension with PTFE and HDPE filters, which can be attributed to preferential interaction of the surfactant with the fluoropolymer construction and the high density polyethylene construction," said Tsuzuki.
In future work, the Pall engineers plan to use UV absorption to confirm that the surfactant has not been effected with Nylon 6,6 membranes, by directly measuring the surfactant concentration in the developer.
In another phase of this work, the engineers dispensed an ethyl lactate solvent into a PTFE container, using a state-of-the-art pump and PTFE and Nylon 6,6 filters, in an attempt to understand how microbubble formation relates to nonaqueous solutions, such as solvents commonly used in resist precoat applications and as base solvents for photoresists. "While solvents typically have lower surface tensions than aqueous fluids such as developers, the low CWST of certain membranes can cause microbubbles to adhere to the membrane and thereby act as a nucleation site for microbubbles, allowing microbubbles to increase in size and be released upon dispense," said Tsuzuki.
Tsuzuki said test results showed the rate of decrease in the level of microbubbles is much faster for Nylon 6,6 than PTFE filters. It took ~40min for the Nylon 6,6 filter to reach a baseline level of <10N/mL, while the PTFE filter did not reach <10N/mL. In addition to a slower rate of decay in counts compared to Nylon 6,6, a number of increases in counts were observed. This can be attributed to the collection of microbubbles on the PTFE membrane surface and subsequent release. In contrast, the Nylon 6,6 membrane demonstrated a continued decrease in counts without any spikes. These data reflect total microbubbles in the volume dispensed as opposed to surface defects on a spun-on wafer. — P.B.
Trikon's low-k etch meets ITRS 2004 requirement
A high-density plasma etch system made by Trikon Technologies, Newport, UK, was used to etch 0.1µm diameter, 7:1 aspect ratio features through Trikon's low-k Flowfill dielectric material (see figure). This version of Flowfill had a dielectric constant of 2.7, and Trikon claims that this is the smallest feature yet etched in a low-k dielectric material. The work, part of a collaboration with International Sematech, was accomplished on Trikon's Omega 201 M0RI high-density plasma etch system with CF4/CH2F2 process chemistry, using a CARL bilayer resist scheme originally developed by Infineon Technologies and Clariant GmbH.
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0.1µm diameter features etched through Trikon's Flowfill dielectric material (ka2.7) after resist strip. (Source: Trikon Technologies)
Trikon also announced that its low-k material has attained a dielectric constant down to 2.4 for 0.1µm technology node designs. Dave Thomas, Trikon's etch product marketing manager, pointed out that the type of low-k structures demonstrated are not planned for DRAM production until 2004, according to the ITRS. The k=3.3 version of the material is in production, and a k=2.8 version is in qualification now. The etch system used is especially appropriate for etching dielectric stacks containing low-k materials, according to Thomas, because it can operate in multiple modes — a high-density 'helicon' mode, a medium-density magnetically-enhanced RIE mode, or a downstream mode. — J.D.
SRC recognizes Shadman for leadership in environmental improvement
Farhang Shadman, professor of chemical engineering at the University of Arizona, Tucson, has received Semiconductor Research Corp.'s (SRC) Landmark Innovation Award for his research in environmentally benign semiconductor manufacturing. The award recognizes programs funded by the SRC resulting in patented inventions that have made a long-term contribution to the semiconductor industry. Specifically, Shadman won the award for his research into reduction of water and energy consumption and purification of water and gases in semiconductor manufacturing.
"His research has improved the environmental safety of semiconductor manufacturing processes and saved the industry several millions of dollars," said Larry Sumney, president and CEO of SRC.
In the area of water and energy use reduction in semiconductor fabs, the research under Shadman's direction has concentrated on three development goals:
- new technology to improve the efficiency of rinsing associated with front-end surface preparation and post-CMP cleaning,
- novel tools and techniques to design and control water purification and wastewater recovery and recycle in semiconductor fabs, and
- novel low-energy and low-chemical purification techniques for treatment and recycling of wastewater.
Some of the practical results of this work include an ultra-pure water (UPW) simulator tool licensed to Sematech for commercialization and a catalytic membrane purification process that integrates the removal of organics, silica, and particles using very low energy (see figure). The latter technology has been licensed to Pall Corp. for commercialization.
In an exclusive interview with Solid State Technology, Shadman explained, "When looking at a large number of process steps in a complex manufacturing environment, instead of trying to optimize them separately we are finding ways to integrate them and create synergy, resulting in higher efficiency, better performance, lower cost, and environmental gain." Another example involves water-use reduction, recovery, and recycling. "Here, our focus has been on treating rinse and recycle as components of an integrated system. This approach eliminates the need for excessive reduction of rinse water or unnecessary and risky attempts to recycle when the measures are not a net environmental gain."
Shadman serves as director of the NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing (see table p. 42), a consortium including the University of Arizona, MIT, Stanford, UC-Berkeley, Cornell University, and Arizona State University. "Environmental factors are not usually included in the design and development of new tools and processes, but we are seeing some slow change."
Shadman believes that — to match today's unprecedented rate of technology change as well as goals in the semiconductor industry — we are going to see the introduction of a large number of new chemicals and processes in both R&D and manufacturing, "far greater than anything we have seen before." He cautions, "We need to consider the environmental, safety, and health aspects of these new chemicals the same way we consider cost and performance factors. This is not just for good citizenship, but needed to avoid excessive cost and potential obstacles to growth. It is a lot easier and less costly to consider and implement alternatives in R&D than to find chemistry or process alternatives when the tools and processes are already in the installed base.
"Integrating environmental technology into the design of processes and tools is the technical driver and the common theme of the Center's research," said Shadman.
New option for PFC reduction during chamber cleaning
Current strategies for controlling the emission of PFCs during the cleaning of CVD chambers include using NF3 and C2F6 gases for the process. (See article on p. 103 by Andrew Johnson et al. of Air Products for more information on these approaches.) Recent work by DuPont shows that a new option, C4F8, can provide the benefits of both of these options.
In a paper given at Semicon Southwest in October 2000, Chuck Allgood and Susan Hsu of DuPont Electronic Gases, and co-authors from International Sematech compared the performance of NF3 and the fluorocarbons C2F6, C3F8, and C4F8. This work was done with an Applied Materials P-5000 DxL oxide deposition tool, extending previously published work on a Novellus PECVD tool. NF3 performed the best in terms of clean time, emissions, and weight of gas used, but C4F8 was the best fluorocarbon and was not far behind NF3 performance. Its appeal is primarily low cost/clean, while achieving performance nearly as good as NF3. NF3 is typically about five times more expensive than the fluorocarbons, and C4F8 is less expensive than other fluorocarbons/clean because the optimized C4F8 process uses a higher fraction of O2.
C4F8 is used primarily in a very high-purity form for high-density plasma (HDP) etching, and this form of the gas is more expensive than other fluorocarbons. However, DuPont will be making a cleaning grade of C4F8 with cost comparable to C2F6. This will soon allow cleaning with nearly the effectiveness of NF3 while maintaining the low cost of C2F6. —J .D.
SOI conference touts novel devices, 3D structures
In the IEEE Electron Devices Society International SOI Conference's novel device session, presenters discussed unique methods for making double gate — or gate-all-around — transistors. Taichi Su, of Purdue University's school of electrical and computer engineering, presented a process for making planar self-aligned double-gate SOI P-MOSFETs. This process uses an epitaxy lateral overgrowth (ELO) method to produce so-called SOI islands (Fig. 1). The SOI island process is key to building the device channel and ultimately, the self-aligned double-gate MOSFETs. Su and his colleagues also used a vertical seed ELO method to form part of the source/drain contacts.
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Figure 1. Purdue Univ. researchers used an epitaxial lateral overgrowth method to develop an SOI region for a double-gate device. In the process, a low-temperature oxide layer is patterned to create recess oxide wells and seed windows (a, b), a selective epitaxy growth process to fill the seed windows and (c), by growing the single crystal silicon laterally, the oxide wells. A CMP step removes excess silicon above the oxide wells, (d) leaving the ELO SOI islands. (Source: Su, Purdue University)
Su said devices using this process could be scaled down to 50nm, and potentially even further. "Due to the uniformity of our CMP equipment and the selectivity of slurry chemistry, I don't think we [at Purdue] can go much further than that. But the industry has not tried to fabricate silicon thin film in this way," he said. "I expect they can do a better job than us if they try."
 Figure 2. A schematic diagram of a 3D IC structure. (Source: V. Chan, Hong Kong University of Science and Technology) |
In producing their gate-all-around transistors (GAT), researchers from Hong Kong University of Science and Technology said they used a metal-induced lateral crystallization (MILC) method that recrystallizes amorphous silicon to form large grain silicon film. Presenter Victor Chan said the MILC process resulted in GAT devices suitable for high performance, low voltage, low power and memory applications. Chan and his colleagues also used the MILC process in building three-dimensional (3D) circuits — touted as a way to extend current CMOS technology — on SOI and bulk wafers.
In their work, the 3D structure incorporated two levels of devices, with PMOS and NMOS devices built on different levels separated by an insulating layer. The first level, in this case the NMOS device, was built on the silicon film of the SOI wafer using conventional CMOS techniques (Fig. 2). The second layer, the PMOS level, was built on top of the first using MILC recrystallization and typical CMOS process steps.
Tech Briefs
Extreme UV and electron projection lithography techniques continue to be the top candidates for commercialization at the 70nm node, according to litho experts who gathered at International Sematech's recent one-day next generation lithography (NGL) workshop in Reston, VA. The consensus reached among 150 lithographers reaffirms the development path identified at the previous NGL workshop, held in December 1999.
"This decision is particularly important as NGL technology moves out of the R&D arena into the supplier area and the infrastructure needs to be prepared," said Gerhard Gross, International Sematech's lithography director. "We know suppliers have precise plans to come up with the tools," he said, but infrastructure development — a focus for International Sematech going forward — is needed. Infrastructure development for costly masks will be a priority. "Mask cost is one of the top critical issues [in all NGL methods]," said Gross.
The next workshop, tentatively scheduled for September 2001, will include a maskless lithography component to meet growing interest in maskless litho techniques, such as a multiple e-beam direct write approach in which hundreds or thousands of paralleled e-beams are used, for possible insertion at the sub-50nm node. —C.L.
Rodel executives recently showed off the capabilities of the company's new, fully operational Materials Integration Center in Phoenix, AZ, which is equipped with four CMP platforms — a Peter Wolters PM 200 Gemini rotational polisher, a Speedfam-IPEC 676 orbital polisher, a Lam Teres linear belt polisher, and an Applied Materials Obsidian 501 web polisher.
In addition, it includes a full array of CMP metrology and cleaning options. The center is approximately 15,000 ft2, including 2000 ft2 of Class 10 cleanroom and 3000 ft2 of Class 1000 cleanroom. Rodel's vested interest is a site where its customers can simulate their processes of record and next generation processes, noted Mario Stanghellini, VP and GM of Rodel's CMP business unit. "The center features an array of systems from top-tier semiconductor equipment manufacturers to support the development of current and future CMP applications. While this is a grand opening of sorts, our center is really an on-going project because we will continue with additions that replicate our customers' needs," he said. Plans call for additions of copper electroplating, and polishing, cleaning, and metrology equipment, as they become available. — P.B.
M is for Manufacturing
TI's Yoshio Nishi and Bob Doering have teamed up as editors of the new Handbook of Semiconductor Manufacturing Technology, recently published by Marcel Dekker (www.dekker.com) after more than two years in the planning. "There's something [in the book] for almost anybody in the fab. It is really manufacturing with a big M, and it goes beyond process technology," says Doering. The editors pulled together a diverse list of chipmaking experts to author individual chapters on current and next generation process technologies — everything from
CVD and etch to low-k dielectrics and e-beam lithography. Contributors came from all parts of the industry: fabs, tool companies, academia, consortia, and research firms.
"We certainly didn't want to make it the 'Handbook according to TI,'" Doering notes. The Handbook also includes chapters on process improvement (yield modeling and management, for example), and a closing chapter from VLSI Research president Dan Hutcheson on chipmaking economics — "the bottom-line when you talk about manufacturing," says Doering. —C.L.