System-on-a-chip: Not as easy as it looks
11/01/2000
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Long ago, a chip architect pointed out to me that the only thing integrated circuits are about, really, is packaging. The more you can squeeze onto the chip, the less you need to play with wires, pins, bonds, and other packaging features that could raise assembly costs and lower reliability. You get better performance and much lower cost/function out of it, too. The level of integration is constrained, however, because putting too much on one chip can make that chip too large. This would mean fewer chips/wafer and lower yield, since it's more likely to find at least one killer defect on a larger piece of silicon. That's the kind of problem that sank early efforts in what was called "wafer-scale integration."
As the shrink has progressed in its steady, semilog cadence over the decades since, it has seemed obvious that the upshot would be we could finally put ALL of the circuitry onto one chip — a total system-on-a-chip, an SOC or system LSI. At last the industry is reaching the point where this is possible. Yet, as many companies have begun to consider this opportunity, they often as not have backed off. It turns out that, as the industry reaches new levels of complexity, other factors beside packaging enter into the equation.
One problem is the mix of processes needed to put too many functions onto the same chip. If the system requires SRAM, DRAM, processors, logic, modem, buses, analog circuitry with A/D and D/A converters, and other functions, too many processing steps and conflicting requirements, like both low-k and high-k dielectrics, along with isolation between functions, make the design and manufacture unwieldy. It's hard to optimize all of the different functions at once; processing costs may get too high, and the chip may get too big.
Even if you can make one, how do you test a chip like this, especially if all the leads must come off the edges? Adding enough built-in test eats up real estate needed for all the system functions. Even though it may be possible to test it completely, it may take far too long. One way around this is to design the functional blocks so they can be isolated from other sections, and thus a number of blocks might be tested simultaneously. But this adds more design complexity. Driving large amounts of logic could entail huge current spikes, and this could heat the chip and affect its performance. So testing can become a limiting factor in how much of a system is best to put onto a single chip.
The result is that many SOC projects evolve instead into a partitioning of the system into two or three or more chips. Each might be made smaller, and the combination could be densely packed on a ceramic substrate to maintain high performance. This assembly can be packaged as if it's an individual chip. Work is progressing on concepts for what can be called "system-in-a-package."
One potential solution is to stack chips one on top of the other and interconnect them along their edges. Rolm in Japan puts different types of chips, such as SiGe and flash memory, face to face and connects them using a technique called Real Socket. This would be even more effective if vias could be drilled right through the silicon to allow interconnect between stacked chips, a solution being explored by Tru Si, for example. Eventually this might lead to chips with circuitry on both the top and bottom.
As processing speeds move into the GHz range, it's essential to get multiple chips as close together as possible to minimize delays along the interconnects. Putting everything onto one chip would be the ultimate solution. If the choice is to partition into two or three chips, then new packaging concepts will be essential. Even though other factors beyond packaging are entering into the decision about putting everything onto a single chip, when multiple chips are the option chosen, packaging may again come into play to resolve other issues.
Since there are problems with putting everything on a single chip, all the efforts to find viable alternatives are valuable. Packaging is certainly a central issue, but it's not the whole story. Overriding everything is chip economics. As an assortment of options become available, different choices will be made depending on requirements for performance, testing costs, potential volume for the chips, time-to-market, and similar considerations. Sometimes, particularly in the communications area where technologies are evolving and standards develop slowly, some part of the design may need to be done in programmable logic so it can be modified later. This is not very amenable to the total SOC approach.
System-on-a-chip is a great idea theoretically, and indeed in some cases we may already have reached this ultimate goal. There are many bypaths, however, that still need to be explored to provide viable alternatives when the SOC approach is too costly or clumsy. As we find out about them, we'll keep you posted.
Many bypaths still need to be explored to provide viable alternatives when the SOC approach is too costly or clumsy.
Robert Haavind
Editor in Chief