Technology News
11/01/2000
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Reticle inspection enters the deep-UV
At a discreet dinner prior to the 20th annual BACUS Symposium on Photomask Technology, KLA-Tencor unveiled to select customers its first reticle inspection technology that uses deep-ultraviolet (DUV) light. In a sense, KLA-Tencor leap-frogged its own leadership in the reticle inspection market; KLA-Tencor's STARlight systems enjoy a high percentage of adoption in the industry.
The new inspection technology provides a four-fold increase in throughput compared to existing advanced reticle inspection technology and can detect defects as small as 100nm. It provides reticle inspection capability specifically targeting optical proximity corrections (OPC) and phase shift masking (PSM) technologies that are increasingly being used for subwavelength lithography.
Ken Levy, chairman of KLA-Tencor, said, "Four years ago, the industry thought it had until 2007 to figure out how to do 100nm. Today, it is less than 3 years. We have been working hard to uphold our end, facing the challenge of how to inspect OPC and PSM on masks, in collaboration with International sematech. This has been the most costly engineering program that we have ever undertaken. It was a very difficult task, but it is not the end, only the beginning." Reportedly, KLA-Tencor put $150 million into the R&D for this new technology.
The first commercial tools using this technology — fifth-generation TeraStar and TeraScan reticle inspection systems — specifically target OPC and PSM. Lance Glasser, general manager of KLA-Tencor's reticle and photomask inspection division, said, "Until now, photomask and IC manufacturers whose reticles used OPC and PSM have had to make a tradeoff between the risk of missed defects and the increased cycle time and cost associated with thorough reticle inspection."
The "Tera" in the product names reflects an image-computing platform, algorithms, and processing technique capable of inspecting up to terapixels
eticle (1012 pixels). (A high definition computer monitor has only 106 pixels.) This technique aids in finding critical killer defects as small as 100nm on complex reticles, corresponding to wafer geometries of 130nm and smaller fabricated with 248nm and 193nm lithography.
The TeraStar tool uses a unique beam-splitting technology to provide multibeam UV reticle inspection capabilities. It can conduct simultaneously transmitted and reflected (STAR) light inspection for contamination with concurrent die-to-die pattern inspection for detection of pattern defects on the chrome surface of reticles, thereby improving the throughput of previous generation tools. In addition, TeraStar detects defects on both the pellicle surface and backside of reticles in a single operation.
TeraStar is an evolution of KLA-Tencor's STARlight tool. At maximum sensitivity, TeraStar can inspect a standard 6-in. reticle in less than one hour. For less critical layers on the reticle, TeraStar can provide inspection at better than 20 minutes
eticle. TeraStar also supports existing defect data communication links to installed defect repair and defect review systems. The tools will be used for final outgoing inspection in reticle manufacturing and for incoming certification at fabs.
TeraScan (see figure) uses a multiple parallel sensor array illuminated by a nonlinear, crystal frequency-doubled, argon-ion laser to deliver DUV wavelength inspection for die-to-database applications. With the image-computing platform, it achieves a 200 million pixel/sec. inspection rate and enables the use of proprietary algorithms to provide both die-to-die and die-to-database inspection with better than 100nm sensitivity. It also uses parallel optical fibers to carry gigabits of data/second internal to the system for maximum throughput.
It has more than a dozen active control loops to provide nanometer mechanical stability and an active force cancellation system to maintain near-perfect quiet operation on a floating 2000kg granite optical bench.
"Interestingly, cost-effective and accurate inspection of today's advanced reticles requires the same level of computing sophistication that is needed to predict global weather patterns," Glasser said. "The image super computer that we have incorporated into this new technology is as powerful as those used to forecast the weather."
Production shipments of these new systems will begin in early 2001; it is a sure bet that Taiwan's TSMC, which uses a large volume of reticles, will be an early customer.
At the customer dinner, Glasser quipped, "This technology works on smaller minimum linewidths than the best maskmakers in this room can make." —P.B.
Hyundai takes on wafer-level packaging, test with FormFactor license
Wafer-level packaging has been a hot topic at assembly conferences for years now, and it recently took a step toward production lines. Hyundai Electronics Industries, Ichon, Korea, has licensed the wafer-level packaging and test processes of FormFactor, Livermore, CA, for use with Hyundai's DRAMs.
The key to FormFactor's wafer-level process is the "MicroSpring" that is formed on each bond pad of each die. The MicroSpring is formed with standard wire bonding equipment that attaches a wire, creates a particular shape, and leaves behind a short spring in an application-dependent shape. The wire is made of standard thermosonically bonded Au. After it is attached, it is plated with Ni alloys to make a robust spring, and then with a final Au layer for good electrical contact and resistance to oxidation. This process can be also accomplished with ribbon instead of round wire, or with two wires on each pad. Since the contacts are independent, unlike some other wafer-level packaging technologies, they are much more compliant and can tolerate the deviations from planarity that can occur with PCBs or other packaging materials. Most other wafer-level technologies under development are actually extensions of wafer fab processes, but FormFactor's approach — the one making strides toward volume production — is based on mature assembly processes.
The largest advantage of FormFactor's approach, though, is the true wafer-level test capability, according to John Novitsky, VP of business development at FormFactor. "Without an effective and economical whole-wafer test method, any wafer-level package approach fails the crucial test for a wafer-based process — scalability," says Novitsky. FormFactor's wafer-level test flow consists of mating a test contactor to the wafer populated with MicroSprings. The whole system can be loaded into a burn-in oven, or long-cycle testing can be performed. FormFactor has developed a wafer-level contactor with a coefficient of thermal expansion close to that of silicon, and this feature plus the compliant spring contacts effectively eliminates the thermal expansion issues that would plague some other wafer-level test approaches. The short springs also provide good electrical performance, and, due to the elimination of the parasitics of test sockets and fixturing, they can eliminate the need for test guardbands.
Novitsky emphasized the significance of Hyundai — the highest volume DRAM manufacturer — licensing this technology. Any cost and yield hits are magnified by the volumes. DRAMs are a good target product for wafer-level approaches, though, because products with low wafer yields lose the scaling advantage of wafer-level packaging and test. Also, the relatively low DRAM pincount avoids the situation where fan-out to an area greater than the die size is required to connect to the board, which would prohibit any wafer-level packaging approach. —J.D.
LG.Phillips' TFT LCDs: Low-temp polysilicon with fewer masks
LG.Philips LCD, Seoul, South Korea, has devised a low-temperature polysilicon process for thin-film transistor (TFT) LCDs based on p-channel MOS (PMOS) technology. Gate drivers, sampling circuits, and pixel switches are fabricated using fewer than seven masks.
Several LCD manufacturers have low-temperature polysilicon (LTPS) processes. The higher carrier mobility of polysilicon versus amorphous silicon (a-Si:H) transistors is important for increasing the transparent aperture area of high-pixel density LCDs. LTPS devices also have sufficient bandwidth for drive control and self-test circuitry to be fabricated on glass. The increased level of on-glass integration reduces the number of external ICs and connections required for system integration.
 Buried-bus coplanar transistor, using PMOS LTPS technology. (Source: LG.Philips LCD) |
However, the high-bandwidth CMOS devices typically require process flows using nine or more masks, according to David Barnes, director of competitive analysis at LG.Philips LCD. Experiments by LG.Philips showed that a five-mask process could create p-channel LTPS transistors having an order of magnitude more mobility than a-Si:H transistors, which is sufficient to deliver a bright, high-resolution display. Negative-channel MOS (NMOS) devices could provide approximately twice the nominal PMOS mobility of 65cm2/V-sec, but they would require additional process steps. NMOS susceptibility to hot-carrier degradation usually requires lightly doped drain structures and additional doping of the channel for controlling threshold voltage. Fabricating CMOS devices would require extra steps for the n+ region. From a power perspective, the relatively high driving voltage requirement of PMOS transistors was found to be less critical than the current leakage and lower bias-voltage stability of NMOS transistors.
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The figure shows a buried-bus coplanar (BBC) structure created with the five-mask PMOS process. Its main feature is the thick SiO2 insulating layer between source-drain metal and the polysilicon channel. The insulator reduces parasitic capacitance and acts as a thermal barrier during excimer laser crystallization of the channel film, which increases the polysilicon process margin. The difference in the insulation thickness above the buried bus lines and p+ contact regions requires good etch selectivity. A single indium tin oxide (ITO) deposition creates the transparent pixel electrode and makes channel contact.
The larger channel width of PMOS devices affects the amount of transparent electrode space available in each pixel, but monitor displays such as a 15-inch UXGA panel have a pixel pitch of 191mm, allowing ample light transmission. The relatively low leakage of PMOS also reduces the storage capacitor area needed, which compensates for the lower channel mobility. —J.D.
SOC emerges for disk drive electronics
Several announcements and presentations at DiskCon, held September 19-21, in San Jose, CA, highlighted the growing interest in system-on-chip (SOC) solutions to the challenges in disk drive electronics. The many new products were matched by some comments about the slow and selective adoption of SOCs in the market, however.
Marvell Semiconductor, Sunnyvale, CA, introduced three SOC products with various combinations of the chip functions required for disk drives. One product integrates a hard disk controller and Marvell's advanced all-CMOS read channel. Another product adds embedded SRAM. The third product, which will sample in late 2000, adds two CPUs, one for system overhead and the other for servo functions. The read channel in this product will also shrink feature sizes to 0.18mm. Marvell said the SOC platform will last for multiple product generations, which would accelerate time-to-market for future products. They saw SOC solutions being driven in many cases by form factor constraints, citing the 1-in. format drives now available. Palmchip, San Jose, CA, a provider of SOC IP integration architecture exhibiting at the show, also said that time-to-market advantages can be found with an established and proven SOC platform. People at both Marvell and Palmchip said the industry is moving toward SOC, but it is a slow process.
LSI Logic, Milpitas, CA, took a step toward offering SOCs for the hard disk drive market by introducing a high performance read channel technology, a new offering from LSI Logic made possible by the acquisition of DataPath Systems in July 2000. The next generation read channel to be offered in 2001 will be both a stand-alone channel and an embedded core for SOC. They expect this to support the bandwidth requirements of the enterprise market and the disk density requirements of the mobile and desktop markets. This strategy was questioned, though, in a presentation by Nersi Nazari, VP of signal processing technology at Marvell. Nazari said that SOC "cannot be done economically for enterprise applications, because enterprise drives need to go to production with the latest read channels." He also believes that SOC integration requires a mature read channel that can be used as a building block. It remains to be seen if a "next generation" of a read channel is mature enough to allow SOC to work economically. Nazari did see SOC being applicable to most desktop and mobile applications, with cost savings, board shrinks, and built-in power saving strategies as some of the key advantages.
John Harris, strategic marketing manager at the Lucent Technologies Microelectronics Group, Allentown, PA, echoed the need to choose SOC applications wisely. He cited the same advantages, but said "SOCs can have compelling economics, but costs must be scrutinized on a case-by-case basis." Harris also described a modular process for SOCs that minimizes the number of extra masks (usually four or fewer) beyond the core CMOS platform to integrate other functions. He also reiterated Nazari's assertion that the read channel is the key piece of IP for any disk drive SOC. —J.D.
Dual side alignment capability in stepper for MEMS applications
Ultratech Stepper, San Jose, CA, has introduced the 1600DSA stepper that uses an off-axis machine vision system to provide dual side alignment (DSA) capability for the MEMS arena. Ultratech believes that the DSA capability will allow it to compete in a market segment that has been dominated by contact aligners.
As the MEMS market matures, an increasing number of applications will require dual side alignment in a high volume manufacturing environment.
A stepper that can process both sides of the wafer can offer significant improvements over contact aligners, according to Fabio Consentino, Ultratech's product business manager for the microsystems market. "Contact/proximity aligners face some difficulties with yield, especially due to the 'contact' lithography approach, which can introduce defects on the mask and the manufacturers' final products," said Consentino. "This limitation will become even more critical when microsystems manufacturers transition from R&D to production, and yield and automation issues become extremely important."
Consentino noted that contact aligners require frequent mask cleaning and periodic replacement, while stepper reticles require little maintenance and provide pellicle protection. Also, in certain situations, contact printing reduces the available real estate on the wafer, which decreases the total number of devices produced per wafer.
At high-dose exposures, the 1600DSA system achieves >1000mW/cm2 irradiance at the wafer plane, which is a useful capability for the thick resist often found in MEMS applications. Specially tailored software and hardware also address the needs of high-topography wafers and thick resists. A newly designed chuck, pre-aligner, and robotic loader were introduced to handle substrates when coated on both sides of the wafer.
The system uses a Windows NT-based operating system, allowing for networking options, such as built-in SECS II communication. —J.D.
New characterization of copper corrosion
Combinatorial experimentation (i.e., multiple experiments occurring simultaneously and under the same conditions) at Sandia National Laboratories, Albuquerque, NM, has shown that copper corrosion in electronic circuitry slows when the metal is implanted with indium and speeds up when implanted with deuterium.
Researchers at Sandia are using micro-combinatorial techniques, specifically multiple corrosion experiments on a single silicon wafer, to more efficiently characterize copper corrosion. Charles Barbour, project principal investigator at Sandia, says, "Use of the small samples proved beneficial because the extent of corrosion could be easily monitored as a function of time and because all of the experiments could be simultaneously performed."
Barbour notes, "In the past, whenever we did copper corrosion tests, we would put a piece of the copper into an atmospheric chamber and add ppm levels of contaminants. This serial approach was very time intensive, and we were unsure that the environment was the same experiment to experiment, making it difficult to compare results." Simultaneous to running the new experiments, these researchers are using the Labs' supercomputing capabilities to calculate how copper would react to impurities actually used in the experiments.
"The computational modeling shows our experimental approach is on the right track," says Barbour. — P.B.
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Morgan talks, BACUS listens
Applied Materials CEO James Morgan offers advice on customer commitment, investment risk, and avoiding the "diode mind." See BACUS show coverage, page 45.
Tech Briefs
LumiLEDs Lighting, San Jose, CA, the joint venture between Agilent Technologies (formerly part of Hewlett-Packard) and Philips Lighting, has announced a breathtaking milestone: the brightness of some of their light emitting diode (LED) products, notably 610nm (orange-red) fabricated with MOCVD, has reached a value of 100 lumens/W output. This is a higher efficiency than fluorescence light bulbs. LumiLEDs also announced that its green and blue InGaN-based LEDs from the same MOCVD technology is already 50 lumens/W. These announcements were made at the IEEE Advanced Concepts in Devices conference held in August at Cornell, NY. The lighting materials in the LEDs are compound semiconductors synthesized using MOCVD technology in reactors from AIXTRON AG, Aachen, Germany. This achievement has long been thought to be difficult to reach, and comes much earlier than expected in industry. — P.B.
Taiwan foundry TSMC said production of its 0.13mm process will begin in the fourth quarter, following tapeouts of customer products using several variations of the process in September. The foundry's 0.13mm process incorporates eight layers of copper and IMD low-k materials (with k = 2.5-3.6). TSMC, however, is still evaluating the low-k options for materials with dielectric constants below 3.6, said Sheldon Wu, TSMC North America senior director for field technical support; initial 0.13mm devices will use FSG. In addition, while TSMC has used 193nm lithography for its 0.13mm work, Wu said the company is evaluating whether it will use 248nm lithography or 193nm lithography for mass production. "We need to consider manufacturing efficiency, tool set availability, capacity requirements ... there are many different factors to consider for volume manufacturing," he said. — C.L.